PIMXRT516SCVM5A datasheet(33/124 Pages) NXP

33 / 124 page

Electrical characteristics

i.MX RT1160 Crossover Processors Data Sheet for Consumer Products, Rev. 0, 04/2021

NXP Semiconductors

Figure 4. Power sequence

4.2.1.1

Power-up sequence

The below restrictions must be followed:

•

VDD_SNVS_IN supply must be turned on before any other power supply or be connected

(shorted) with VDD_LPSR_IN and DCDC_IN supply.

•

If a coin cell is used to power VDD_SNVS_IN, then ensure that it is connected before any other

supply is switched on.

•

When internal DCDC is enabled, external delay circuit is required to delay the

“DCDC_PSWITCH” signal at least 1 ms after DCDC_IN is stable.

•

Need to ensure DCDC_IN ramps to 3.0 V within 0.2 x RC, RC is from external delay circuit used

for DCDC_PSWITCH and must be longer than 1 ms.

•

POR_B (if used) must be held low during the entire power up sequence.

NOTE

The POR_B input (if used) must be immediately asserted at power-up and

remain asserted until after the last power rail reaches its working voltage. In

the absence of an external reset feeding the POR_B input, the internal POR

module takes control. See the i.MX RT1160 Reference Manual

(IMXRT1160RM) for further details and to ensure that all necessary

requirements are being met.

NOTE

The voltage on DCDC_PSWITCH pin should be below 0.5 V before

ramping up the voltage on DCDC_PSWITCH.

VDD_SNVS_IN

VDD_SNVS_ANA

VDD_SNVS_DIG

VDD_LPSR_IN

VDD_LPSR_ANA

VDD_LPSR_DIG

DCDC_IN

VDDA_1P8

VDD_SOC_IN

1ms

DCDC_PSWITCH

POR_B

ONOFF

PIMXRT516SCVM5A Datasheet(PDF) 33 Page - NXP Semiconductors

PIMXRT516SCVM5A Datasheet(HTML) 33 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL