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PIMXRT516SCVM5A Datasheet(PDF) 66 Page - NXP Semiconductors |
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PIMXRT516SCVM5A Datasheet(HTML) 66 Page - NXP Semiconductors |
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66 / 124 page  i.MX RT1160 Crossover Processors Data Sheet for Consumer Products, Rev. 0, 04/2021 66 NXP Semiconductors Electrical characteristics 4.6.1.3 MIPI LP-RX specifications 2 Though there is no specified maximum for Z OLP, the LP transmitter output impedance ensures the TRLP/TFLP specification is met. Table 63. MIPI low-power transmitter AC specifications Symbol Parameter Min Typ Max Unit TRLP /TFLP 1 1 C LOAD includes the low equivalent transmission line capacitance. The capacitance of TX and RX are assumed to always be < 10 pF. The distributed line capacitance can be up to 50 pF for a transmission line with 2 ns delay. 15% to 85% Rise Time and Fall Time — — 25 ns TREOT 1,2,3 2 The rise-time of T REOT starts from the HS common-level at the moment of the differential amplitude drops below 70 mV, due to stopping of the differential drive. 3 With an additional load capacitance C CM between 0 to 60 pF on the termination center tap at RX side of the lane. 30% to 85% Rise Time and Fall Time — — 35 ns TLP-PULSE-TX 4 4 This parameter value can be lower than T LPX (MIPI D-PHY low power states), due to differences in rise vs. fall signal slopes, trip levels, and mismatches between Dp and Dn LP transmitters. Any LP exclusive-OR pulse observed during HS EoT (transition from HS level to LP-11) is glitch behavior as described in Low-Power Receiver section. Pulse width of the LP exclusive-OR clock: First LP exclusive-OR clock pulse after Stop state or last pulse before Stop state 40 — — ns Pulse width of the LP exclusive-OR clock: All other pulses 20 — — ns TLP-PER-TX Period of the LP exclusive-OR clock 90 — — ns V/t SR 1,5,6,7 5 When the output voltage is between 15% and 85% of the fully settled LP signal levels. 6 Measured as average across any 50 mV segment of the output signal transition. 7 This value represents a corner point in a piecewise linear curve. Slew Rate @ CLOAD = 0 pF 30 — 500 mV/ns Slew Rate @ CLOAD = 5 pF 30 — 200 mV/ns Slew Rate @ CLOAD = 20 pF 30 — 150 mV/ns Slew Rate @ CLOAD = 70 pF 30 — 100 mV/ns CLOAD 1 Load Capacitance 0 — 70 pF Table 64. MIPI low power receiver DC specifications Symbol Parameter Min Typ Max Unit VIH Logic 1 input voltage 880 — 1300 mV VIL Logic 0 input voltage, not in ULP state — — 550 mV VIL-ULPS Logic 0 input voltage, ULP state — — 300 mV VHYST Input hysteresis 25 — — mV Table 65. MIPI low power receiver AC specifications Symbol Parameter Min Typ Max Unit eSPIKE 1,2 Input pulse rejection — — 300 V.ps |
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