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MCP3464 Datasheet(PDF) 65 Page - Microchip Technology

Part # MCP3464
Description  Two/Four/Eight-Channel, 153.6 ksps, Low Noise, 16-Bit Delta-Sigma ADC
PDF  108 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP3464 Datasheet(HTML) 65 Page - Microchip Technology

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 2019-2021 Microchip Technology Inc.
DS20006180D-page 65
MCP3461/2/4
6.4
Reading from the Device
When the Command bit, CMD[0], is equal to ‘1’, the
command is a read communication. After the STATUS
byte has been transferred, the first register to be read
on the SDO pin is the one with the address defined by
the Command Address bits (CMD[5:2]).
Any CS rising edge during a read communication
aborts the current reading.
The registers may need 4, 8, 16, 24 or 32 bits to be fully
read, depending on their address (see Table 8-1).
If the CMD[1:0] bits are equal to ‘11’, the command type
is incremental read. In this case, after each register is
read, the Address Pointer is automatically incremented
as long as CS stays logic low. The following data bytes
are read from the next address sequentially defined in
the register map. When the Address Pointer reaches
0xF (last register in the register map for reading), the
next register to read is the register 0x0. See Figure 6-7
for a graphical representation of the address looping.
FIGURE 6-7:
Incremental Read Loop.
If the CMD[1:0] bits are equal to ‘01’, the command
type is static read. In this case, the register address
defined in the COMMAND byte is read continuously.
The Address Pointer is not incremented automatically.
Continuously clocking SCK while CS stays logic low
will continuously read the same register. Reading
another register is only possible by aborting the current
communication sequence by raising CS and issuing
another command.
In both Static and Incremental modes, the registers will
be updated after each register read is fully performed.
If the value of the register changes internally during the
read, it will only be updated after the end of the read.
The value of each register is latched in the SDO Output
Shift register at the first rising edge of SCK of each
individual register reading. Figure 6-8 shows the details,
bit by bit, of a single register read communication.
Figure 6-9 shows the examples of static and incremen-
tal read communications.
CONFIG0 (0x1)
CONFIG1 (0x2)
CONFIG2 (0x3)
CONFIG3 (0x4)
IRQ (0x5)
MUX (0x6)
SCAN (0x7)
TIMER (0x8)
OF FSETCAL (0x9)
GAINCAL (0xA)
Reserved (0xB)
Reserved (0xC)
LOCK (0xD)
Reserved (0xE)
CRCREG (0xF)
ADCDATA (0x0)



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