PIMXRT516SCVP5A datasheet(20/124 Pages) NXP

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i.MX RT1160 Crossover Processors Data Sheet for Consumer Products, Rev. 0, 04/2021

NXP Semiconductors

Modules list

3.1

Special signal considerations

Table 4 lists special signal considerations for the i.MX RT1160 processors. The signal names are listed in

alphabetical order.

The package contact assignments can be found in Section 6, Package information and contact

assignments.” Signal descriptions are provided in the i.MX RT1160 Reference Manual

(IMXRT1160RM).

XECC

External ECC Controller

Memories and

Memory Controllers

XECC can be used as a gasket module on AXI bus to

support ECC function for external memory.

XRDC

Extended Resource

Domain Controller

Security

The XRDC provides an integrated, scalable

architectural framework for access control, system

memory protection, and peripheral isolation. It allows

software to assign chip resources including processor

cores, non-core bus masters, memory regions, and

slave peripherals to processing domains to support

enforcement of robust operational environments.

Table 4. Special signal considerations

Signal Name

Remarks

CLK1_P/ CLK1_N

This differential output is reserved for NXP internal use. For users, this output must be a no

connect.

DCDC_PSWITCH

PAD is in DCDC_IN domain and connected to ground to bypass DCDC.

To enable DCDC function, assert DCDC_IN with at least 1ms delay for DCDC_IN rising edge.

RTC_XTALI/RTC_XTALO To hit the exact oscillation frequency, the board capacitors must be reduced to account for the

board and chip parasitics. The integrated oscillation amplifier is self-biasing, but relatively weak.

Care must be taken to limit the parasitic leakage from RTC_XTALI and RTC_XTALO to either the

power or the ground (> 100 M). This de-biases the amplifier and reduces the start-up margin.

If you want to feed an external low-frequency clock into RTC_XTALI, the RTC_XTALO pin must

remain unconnected or driven by a complementary signal. The logic level of this forcing clock must

not exceed the VDD_SNVS_DIG level and the frequency shall be < 100 kHz under the typical

conditions.

It is recommended to tie RTC_XTALI to GND if external crystal is not used. When a high-accuracy

real-time clock is not required, the system may use the on-chip 32 kHz oscillator. The tolerance is

10%. The ring oscillator starts faster than the external crystal and is used until the external crystal

reaches a stable oscillation. The ring oscillator also starts automatically if no clock is detected at

RTC_XTALI.

XTALI/XTALO

The SDK software requires 24 MHz on XTALI/XTALO. The crystal can be eliminated if an external

24 MHz oscillator is available in the system. In this case, refer to section of Bypass Configuration

(24 MHz) from the reference manual. There are three configurations that can be utilized, but

configuration 2 is recommended.

The logic level of this forcing clock must not exceed the VDD_LPSR_ANA level.

If this clock is used as a reference for USB, then there are strict frequency tolerance and jitter

requirements. See Section 4.2.6, On-chip oscillators and relevant interface specifications chapters

for details.

Table 3. i.MX RT1160 modules list (continued)

Block Mnemonic

Block Name

Subsystem

Brief Description

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