PIMXRT516SCVP5A datasheet(62/124 Pages) NXP

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i.MX RT1160 Crossover Processors Data Sheet for Consumer Products, Rev. 0, 04/2021

NXP Semiconductors

Electrical characteristics

Figure 22. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1

4.5.2.1.4

DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x3

There are two cases when the memory provides both read data and the read strobe in DDR mode:

•

B1—Memory generates both read data and read strobe on SCK edges

•

B2—Memory generates read data on SCK edges and generates read strobe on SCK2

edges

Figure 23. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case B1)

Table 55. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x1

Symbol

Parameter

Min

Max

Unit

Frequency of operation

—

MHz

TIS

Setup time for incoming data

—

TIH

Hold time for incoming data

—

Table 56. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case B1)

Symbol

Parameter

Min

Max

Unit

Frequency of operation

—

166

MHz

TSCKD - TSCKDQS

Time delta between TSCKD and TSCKDQS

-1

TIS

TIH

TIS

TIH

SCLK

SIO[0:7]

Internal Sample Clock

TSCKD

TSCKDQS

SIO[0:7]

DQS

SCK

PIMXRT516SCVP5A Datasheet(PDF) 62 Page - NXP Semiconductors

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