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CY29976
Document #: 38-07413 Rev. *A
Page 8 of 10
Notes:
7.
Parameters are guaranteed by design and characterization. Not 100% tested in production.
8.
Maximum and minimum input reference is limited by VC0 lock range.
9.
Outputs loaded with 30 pF each.
10. 50
Ω transmission line terminated into V
DD/2.
11. Tpd is specified for a 50-MHz input reference. Tpd is the static phase error of the device and does not include jitter.
12. VCMR = 2.0V and VPP = 650µV. Tpd window will vary with different VCMR and VPP values.
]
AC Parameters:[7] VDD = VDDC = 3.3V ±10%, TA = –40°C to +85°C
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
Tr/Tf
TCLK Input Rise / Fall
3.0
ns
Fref
Reference Input Frequency
Note 8
Note 8
MHz
FrefDC
Reference Input Duty Cycle
25
75
%
Fvco
PLL VCO Lock Range
200
480
MHz
Tlock
Maximum PLL lock Time
10
ms
Tr/Tf
Output Clocks Rise/Fall Time[9]
0.8V to 2.0V
0.15
1.2
ns
Fout
Maximum Output Frequency
Q (
÷2)
-
125
MHz
Q (
÷4)
120
Q (
÷6)
80
Q (
÷8)
60
FoutDC
Output Duty Cycle[9]
45
55
%
tpZL, tpZH
Output Enable Time[9](all outputs)
2
10
ns
tpLZ, tpHZ
Output Disable Time[9](all outputs)
2
8
ns
TCCJ
Cycle to Cycle Jitter[9](peak to peak)
±100
ps
TSKEW
Any Output to Any Output Skew[9,10]
All outputs at same
frequency
350
ps
Outputs at different
frequencies
550
ps
Tpd
Propagation
Delay[10,11]
PECL_CLK[12]
QFB =(
÷8)
–225
–25
175
ps
TCLK0/1
–130
270
Ordering Information
Part Number
Package Name
Package Type
Production Flow
CY29976AI
A52
52-Pin TQFP
Industrial, –40°C to +85°C
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