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3.3V, 125-MHz, Multi-Output Zero Delay Buffer
CY29976
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-07413 Rev. *A
Revised December 27, 2002
76
Features
• Output frequency up to 125 MHz
• Supports PowerPC®, and Pentium® processors
• 12 clock outputs: frequency configurable
• Configurable Output Disable
• Two reference clock inputs for dynamic toggling
• Oscillator or PECL reference input
• Spread spectrum compatible
• Glitch-free output clocks transitioning
• 3.3V power supply
• Pin compatible with SC973X
• Industrial temperature range: –40°C to +85°C
• 52-Pin TQFP package
Note:
1.
x = the reference input frequency, 200MHz < FVCO < 480MHz
.
Table 1. Frequency Table[1]
VC0_SEL
FB_SEL2
FB_SEL1
FB_SEL0
FVCO
0000
8x
0001
12x
0010
16x
0011
20x
0100
8x
0101
12x
0110
16x
0111
20x
1000
4x
1001
6x
1010
8x
1011
10x
1100
4x
1101
6x
1110
8x
1111
10x
Block Diagram
Pin Configuration
VSS
MR#/OE
SCLK
SDATA
FB_SEL2
PLL_EN
REF_SEL
TCLK_SEL
TCLK0
TCLK1
PECL_CLK
PECL_CLK#
VDD
VSS
QB0
VDDC
QB1
VSS
QB2
VDDC
QB3
FB_IN
VSS
FB_O UT
VDDC
FB_SEL0
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
14 15 16 17 18 19 20 21 22 23 24 25 26
52 51 50 49 48 47 46 45 44 43 42 41 40
CY29976
REF_SEL
0
1
0
1
Phase
Detector
VCO
LPF
Sync
Frz
D Q
QA0
Sync
Frz
D Q
Sync
Frz
D Q
Sync
Frz
D Q
Sync
Frz
D Q
Sync
Frz
D Q
Power-On
Reset
Output Disable
Circuitry
Data Generator
/2, /6, /4, /12
/2, /6, /4, /10
/8, /2, /6, /4
/4, /6, /8, /10
Sync Pulse
PECL_CLK
PECL_CLK#
TCLK0
TCLK1
TCLK_SEL
FB_IN
MR#/OE
SELA(0,1)
2
SELB(0,1)
2
SELC(0,1)
2
FB_SEL(0:2)
3
SCLK
SDATA
INV_CLK
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC0
QC1
QC2
QC3
FB_OUT
SYNC
12
VCO_SEL
PLL_EN
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