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MPC755 Datasheet(PDF) 3 Page - NXP Semiconductors

Part # MPC755
Description  MPC755 RISC Microprocessor Hardware Specifications Addendum for the XPC755xxxnnnLE Series
PDF  8 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

MPC755 Datasheet(HTML) 3 Page - NXP Semiconductors

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MPC755 RISC Microprocessor Hardware Specifications Addendum for the XPC755xxxnnnLE Series, Rev. 0.1
Freescale Semiconductor
3
4.2.1
Clock AC Specifications
Table 7. Power Consumption for MPC755
Processor (CPU) Frequency
Unit
Notes
400 MHz
450 MHz
Full-Power Mode
Typical
4.0
4.6
W
1, 3, 4
Maximum
6.0
8.0
W
1, 2
Doze Mode
Maximum
2.3
2.8
W
1, 2, 4
Nap Mode
Maximum
1.0
1.0
W
1, 2, 4
Sleep Mode
Maximum
470
470
mW
1, 2, 4
Sleep Mode (PLL and DLL Disabled)
Maximum
430
430
mW
1, 2
Notes:
1. These values apply for all valid processor bus and L2 bus ratios. The values do not include I/O supply power (OVDD and
L2OVDD) or PLL/DLL supply power (AVDD and L2AVDD). OVDD and L2OVDD power is system dependent, but is typically
<10% of VDD power. Worst case power consumption for AVDD = 15 mW and L2AVDD = 15 mW.
2. Maximum power is measured at nominal VDD (see Table 3) while running an entirely cache-resident, contrived sequence of
instructions which keep the execution units maximally busy.
3. Typical power is an average value measured at the nominal recommended VDD (see Table 3) and 65°C in a system while
running a typical code sequence.
4. Not 100% tested. Characterized and periodically sampled.
Table 8. Clock AC Timing Specifications
At recommended operating conditions (see Table 3)
Characteristic
Symbol
Maximum Processor Core Frequency
Unit
Notes
400 MHz
450 MHz
Min
Max
Min
Max
Processor frequency
fcore
200
400
200
450
MHz
1
VCO frequency
fVCO
400
800
400
900
MHz
1
Note:
1. Caution: The SYSCLK frequency and PLL_CFG[0:3] settings must be chosen such that the resulting SYSCLK (bus)
frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to the PLL_CFG[0:3] signal description in Section 1.8.1, “PLL Configuration
,” for valid PLL_CFG[0:3]
settings.



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