MPC755 RISC Microprocessor Hardware Specifications Addendum for the XPC7n5BxxnnnLD Series, Rev. 2.1

Freescale Semiconductor

5

General Parameters

Table 12 provides the L2 bus interface AC timing specifications for the MPC755 described in this

document when the L2 bus interface is in 3.3 V mode only. The L2 bus interface of the part described

herein is not tested in 1.8 V/2.0 V mode and does not meet these specifications. The L2 interface output

drivers may display a non-linear, stepped behavior when switching that prolongs the rise and fall times in

non-linear behavior results when the driver output impedance is greater than the board impedance and can

cause reflected wave switching instead of incident wave switching. The voltage level at which the step will

the SRAM, the SRAM will not recognize a logical high on a given signal until the reflected wave arrives.

The time delay between the arrival of the incident wave and the reflected wave is determined solely by the

propagation delay of the signal. Because of these issues, Freescale does not recommend or support the use

of the L2 bus interface of the affected part numbers described herein in 1.8 V/2.0 V mode.

Table 12. L2 Bus Interface AC Timing Specifications

At recommended operating conditions (see Table 3)

Parameter

Symbol

300 MHz

350 MHz

400 MHz

Unit

Notes

Min

Max

Min

Max

Min

Max

Setup Times: Data and parity

1.5

—

1.5

—

1.5

—

ns

2

Input Hold Times: Data and parity

0.5

—

0.5

—

0.5

—

ns

2

Valid Times:

All outputs when L2CR[14–15] = 00

All outputs when L2CR[14–15] = 01

All outputs when L2CR[14–15] = 10

All outputs when L2CR[14–15] = 11

—

—

—

—

3.6

3.8

4.0

4.2

—

—

—

—

3.6

3.8

4.0

4.2

—

—

—

—

3.6

3.8

4.0

4.2

ns

3, 4

L2SYNC_IN to high impedance:

All outputs when L2CR[14–15] = 00

All outputs when L2CR[14–15] = 01

All outputs when L2CR[14–15] = 10

All outputs when L2CR[14–15] = 11

—

—

—

—

3.5

4.0

4.2

4.5

—

—

—

—

3.5

4.0

4.2

4.5

—

—

—

—

3.5

4.0

4.2

4.5

ns

3, 5

Notes:

2. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising edge of

the input L2SYNC_IN. Input timings are measured at the pins.

3. All output specifications are measured from the midpoint voltage of the rising edge of L2SYNC_IN to the midpoint of the

signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-

Ω load.

4. The outputs are valid for both single-ended and differential L2CLK modes. For pipelined registered synchronous

BurstRAMs, L2CR[14–15] = 01 or 10 is recommended. For pipelined late write synchronous BurstRAMs, L2CR[14–15] = 11

is recommended.

5. Guaranteed by design and characterization.