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PIMXRT516SCVM2A Datasheet(PDF) 71 Page - NXP Semiconductors |
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PIMXRT516SCVM2A Datasheet(HTML) 71 Page - NXP Semiconductors |
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71 / 124 page  Electrical characteristics i.MX RT1160 Crossover Processors Data Sheet for Extended Industrial Products, Rev. 0, 04/2021 NXP Semiconductors 71 Figure 31. SAI timing—Master modes Table 71. Master mode SAI timing Num Characteristic Min Max Unit S1 SAI_MCLK cycle time 15 — ns S2 SAI_MCLK pulse width high/low 40% 60% MCLK period S3 SAI_BCLK cycle time 40 — ns S4 SAI_BCLK pulse width high/low 40% 60% BCLK period S5 SAI_BCLK to SAI_FS output valid — 8.4 ns S6 SAI_BCLK to SAI_FS output invalid 0 — ns S7 SAI_BCLK to SAI_TXD valid — 10 ns S8 SAI_BCLK to SAI_TXD invalid 1 — ns S9 SAI_RXD/SAI_FS input setup before SAI_BCLK 14 — ns S10 SAI_RXD/SAI_FS input hold after SAI_BCLK 0 — ns Table 72. Slave mode SAI timing Num Characteristic Min Max Unit S11 SAI_BCLK cycle time (input) 40 — ns S12 SAI_BCLK pulse width high/low (input) 40% 60% BCLK period S13 SAI_FS input setup before SAI_BCLK 6 — ns S14 SAI_FA input hold after SAI_BCLK 2 — ns S15 SAI_BCLK to SAI_TXD/SAI_FS output valid — 20 ns S16 SAI_BCLK to SAI_TXD/SAI_FS output invalid -1.5 — ns |
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