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PIMXRT516SCVM2A Datasheet(PDF) 99 Page - NXP Semiconductors |
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PIMXRT516SCVM2A Datasheet(HTML) 99 Page - NXP Semiconductors |
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99 / 124 page  Boot mode configuration i.MX RT1160 Crossover Processors Data Sheet for Extended Industrial Products, Rev. 0, 04/2021 NXP Semiconductors 99 5 Boot mode configuration This section provides information on boot mode configuration pins allocation and boot devices interfaces allocation. 5.1 Boot mode configuration pins Table 97 provides boot options, functionality, fuse values, and associated pins. Several input pins are also sampled at reset and can be used to override fuse values, depending on the value of BT_FUSE_SEL fuse. The boot option pins are in effect when BT_FUSE_SEL fuse is ‘0’ (cleared, which is the case for an unblown fuse). For detailed boot mode options configured by the boot mode pins, see the i.MX RT1160 Fuse Map and the System Boot chapter in i.MX RT1160 Reference Manual (IMXRT1160RM). 5.2 Boot device interface allocation The following tables list the interfaces that can be used by the boot process in accordance with the specific boot mode configuration. The tables also describe the interface’s specific modes and IOMUXC allocation, which are configured during boot when appropriate. Table 97. Fuses and associated pins used for boot Pad Default setting on reset eFuse name Details GPIO_LPSR_02 35 K pull-down BOOT_MODE[0] GPIO_LPSR_03 35 K pull-down BOOT_MODE[1] GPIO_DISP_B1_06 HighZ BT_CFG[0] Boot Options, Pin value overrides fuse settings for BT_FUSE_SEL = ‘0’. Signal Configuration as Fuse Override Input at Power Up. These are special I/O lines that control the boot up configuration during product development. In production, the boot configuration can be controlled by fuses. GPIO_DISP_B1_07 HighZ BT_CFG[1] GPIO_DISP_B1_08 HighZ BT_CFG[2] GPIO_DISP_B1_09 HighZ BT_CFG[3] GPIO_DISP_B1_10 HighZ BT_CFG[4] GPIO_DISP_B1_11 HighZ BT_CFG[5] GPIO_DISP_B2_00 HighZ BT_CFG[6] GPIO_DISP_B2_01 HighZ BT_CFG[7] GPIO_DISP_B2_02 HighZ BT_CFG[8] GPIO_DISP_B2_03 HighZ BT_CFG[9] GPIO_DISP_B2_04 HighZ BT_CFG[10] GPIO_DISP_B2_05 HighZ BT_CFG[11] Table 98. Boot through NAND PAD Name IO Function ALT Comments GPIO_EMC_B1_00 semc.DATA[0] ALT 0 — GPIO_EMC_B1_01 semc.DATA[1] ALT 0 — GPIO_EMC_B2_02 semc.DATA[2] ALT 0 — |
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