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PIMXRT516SCVP5A Datasheet(PDF) 91 Page - NXP Semiconductors

Part # PIMXRT516SCVP5A
Description  i.MX RT1160 Crossover Processors Data Sheet for Extended Industrial Products
PDF  124 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

PIMXRT516SCVP5A Datasheet(HTML) 91 Page - NXP Semiconductors

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Electrical characteristics
i.MX RT1160 Crossover Processors Data Sheet for Extended Industrial Products, Rev. 0, 04/2021
NXP Semiconductors
91
Figure 44 shows MII receive signal timings. Table 89 describes the timing parameters (M1–M4) shown in
the figure.
Figure 44. MII receive signal timing diagram
1 ENET_RX_EN, ENET_RX_CLK, and ENET0_RXD0 have the same timing in 10 Mbps 7-wire interface mode.
4.9.4.1.2
MII transmit signal timing (ENET_TX_DATA3,2,1,0, ENET_TX_EN,
ENET_TX_ER, and ENET_TX_CLK)
The transmitter functions correctly up to an ENET_TX_CLK maximum frequency of 25 MHz + 1%.
There is no minimum frequency requirement. Additionally, the processor clock frequency must exceed
twice the ENET_TX_CLK frequency.
Table 89. MII receive signal timing
ID
Characteristic1
Min.
Max.
Unit
M1
ENET_RX_DATA3,2,1,0, ENET_RX_EN, ENET_RX_ER to
ENET_RX_CLK setup
5—
ns
M2
ENET_RX_CLK to ENET_RX_DATA3,2,1,0, ENET_RX_EN,
ENET_RX_ER hold
5—
ns
M3
ENET_RX_CLK pulse width high
35%
65%
ENET_RX_CLK period
M4
ENET_RX_CLK pulse width low
35%
65%
ENET_RX_CLK period
ENET_RX_CLK (input)
ENET_RX_DATA3,2,1,0
M3
M4
M1
M2
ENET_RX_ER
ENET_RX_EN
(inputs)



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