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MPC885ZP80 Datasheet(PDF) 17 Page - NXP Semiconductors |
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MPC885ZP80 Datasheet(HTML) 17 Page - NXP Semiconductors |
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17 / 87 page  MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor 17 Bus Signal Timing Table 9 provides the timings for the MPC885/MPC880 at 33-, 40-, 66-, and 80-MHz bus operation. The timing for the MPC885/MPC880 bus shown assumes a 50-pF load for maximum delays and a 0-pF load for minimum delays. CLKOUT assumes a 100-pF load for maximum delays and a 50-pF load for minimum delays. Table 7. Frequency Ranges for Standard Part Frequencies (1:1 Bus Mode) Part Frequency 66 MHz 80 MHz Min Max Min Max Core frequency 40 66.67 40 80 Bus frequency 40 66.67 40 80 Table 8. Frequency Ranges for Standard Part Frequencies (2:1 Bus Mode) Part Frequency 66 MHz 80 MHz 133 MHz Min Max Min Max Min Max Core frequency 40 66.67 40 80 40 133 Bus frequency 20 33.33 20 40 20 66 Table 9. Bus Operation Timings Num Characteristic 33 MHz 40 MHz 66 MHz 80 MHz Unit Min Max Min Max Min Max Min Max B1 Bus period (CLKOUT), see Table 7 ———————— ns B1a EXTCLK to CLKOUT phase skew - If CLKOUT is an integer multiple of EXTCLK, then the rising edge of EXTCLK is aligned with the rising edge of CLKOUT. For a non-integer multiple of EXTCLK, this synchronization is lost, and the rising edges of EXTCLK and CLKOUT have a continuously varying phase skew. –2 +2 –2 +2 –2 +2 –2 +2 ns B1b CLKOUT frequency jitter peak-to-peak — 1 — 1 — 1 — 1 ns B1c Frequency jitter on EXTCLK — 0.50 — 0.50 — 0.50 — 0.50 % B1d CLKOUT phase jitter peak-to-peak for OSCLK ≥ 15 MHz —4 —4 —4 —4 ns CLKOUT phase jitter peak-to-peak for OSCLK < 15 MHz —5 —5 —5 —5 ns B2 CLKOUT pulse width low (MIN = 0.4 × B1, MAX = 0.6 × B1) 12.1 18.2 10.0 15.0 6.1 9.1 5.0 7.5 ns B3 CLKOUT pulse width high (MIN = 0.4 × B1, MAX = 0.6 × B1) 12.1 18.2 10.0 15.0 6.1 9.1 5.0 7.5 ns B4 CLKOUT rise time — 4.00 — 4.00 — 4.00 — 4.00 ns |
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