PD39208 datasheet(19/34 Pages) MICROCHIP

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Table 4-3. Manager Broadcast

3 Bits (bit 7:5)

4 Bits (bit 4:1)

1 Bit (bit 0)

001

0000

Write

Figure 4-3. SPI Timing Diagram

Table 4-4. SPI Timing Diagram Description

Name Min Delay

Max Delay

Description

910 ns

SPI clock period

45%

55%

SPI duty cycle

340 ns

SPI_CS setup to SPI clock positive edge (delay after SPI_CS active

signal)

340 ns

SPI_CS hold to SPI clock positive edge (delay before SPI_CS

inactive signal)

2 SPI clock cycles

Delay between last SCK in SPI1 frame and first SCK at adjacent

SPI1 frame

1 SPI clock cycle

Between byte 0 (IC address) and byte 1 (address)

1 SPI clock cycle

Between byte 1 (address) and byte 2 (data)

1 SPI clock cycle

Between byte 2 (MS data byte) and byte 3 (LS data byte)

340 ns

MOSI setup time

D10

340 ns

MOSI hold time

D11

700 ns

MISO tri-state to valid data from clock positive edge

D12

700 ns

MISO valid data to tri-state from SPI_CS positive edge

D13

1 SPI clock cycle

SPI_CS width (Delay SPI1 frame to adjacent SPI1 frame)

D14

60 ns

Filtered glitch width

D15

D3 + D11 + 24

SPI clock

cycles

MISO tri-state from SPI_CS negative edge to valid data

D16

200 ns

MISO setup to SCK positive edge

D17

200 ns

MISO hold to SCK positive edge

PD39208

Application Information

Datasheet

DS00003555B-page 19

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