6.

Memory Organization

The AT24CM02 is internally organized as 1,024 pages of 256 bytes each.

6.1

Device Addressing

Accessing the device requires an 8-bit device address byte following a Start condition to enable the device for a read

or write operation. Since multiple client devices can reside on the serial bus, each client device must have its own

unique address so the host can access each device independently.

The Most Significant four bits of the device address byte is referred to as the device type identifier. The device type

identifier ‘1010’ (Ah) is required in bits 7‑4 of the device address byte (see Table 6‑1).

Following the 4-bit device type identifier is the hardware client address bit, A2. This bit can be used to expand the

address space by allowing up to two Serial EEPROM devices on the same bus. The hardware client address bit

must correlate with the voltage level on the corresponding hardwired device address input pin A2. The A2 pin uses

an internal proprietary circuit that automatically biases the pin to a logic ‘0’ state if the pin is allowed to float. In

order to operate in a wide variety of application environments, the pull‑down mechanism is intentionally designed to

be somewhat strong. Once the pin is biased above the CMOS input buffer's trip point (~0.5 x VCC), the pull‑down

mechanism disengages. Microchip recommends connecting the A2 pin to a known state whenever possible.

Following the A2 hardware client address bit are A17 and A16 (bit 2 and bit 1 of the device address byte), which are

the Most Significant bits of the memory array word address (see Table 6‑1).

The eighth bit (bit 0) of the device address byte is the Read/Write Select bit. A read operation is initiated if this bit is

high and a write operation is initiated if this bit is low.

Upon the successful comparison of the device address byte, the AT24CM02 will return an ACK. If a valid comparison

is not made, the device will NACK.

Table 6-1. Device Address Byte

Package

Device Type Identifier

Hardware Client Address Bit

Most Significant Bits

of the Word Address

R/W Select

Bit 7 Bit 6 Bit 5 Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

All Packages

1

0

1

0

A17

A16

R/W

For all operations except the current address read, two 8‑bit word address bytes must be transmitted to the device

immediately following the device address byte. The word address bytes contain the lower 16 significant memory

array address bits, and are used to specify which byte location in the EEPROM to start reading or writing. See Table

6-2 and Table 6-3 to review their bit positions.

Table 6-2. First Word Address Byte

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

A15

A14

A13

A12

A11

A10

A9

A8

Table 6-3. Second Word Address Byte

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

A7

A6

A5

A4

A3

A2

A1

A0

AT24CM02

Memory Organization

Datasheet

DS20006197C-page 16