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PL560-08 Datasheet(PDF) 5 Page - PhaseLink Corporation

Part # PL560-08
Description  Analog Frequency Multiplier
PDF  15 Pages
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Manufacturer  PLL [PhaseLink Corporation]
Direct Link  http://www.phaselink.com
Logo PLL - PhaseLink Corporation

PL560-08 Datasheet(HTML) 5 Page - PhaseLink Corporation

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Analog Frequency Multiplier
VCXO Family of Products
47745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991
www.phaselink.com
Rev.:03-22-05 Page 5
VOLTAGE CONTROL SPECIFICATION
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
VCXO Stabilization Time
TVCXOSTB
From power valid
10
ms
VCXO Tuning Range
XTAL C0 /C1 <300
200
ppm
CLK output pullability
VCON= 1.65V
± 1.65V
XTAL C0 /C1 <300
±100
±120
ppm
Linearity
5
10
%
VCON input impedance
130
k
Ω
VCON modulation BW
0V < VCON < 3.3V, -3dB
25
kHz
EXTERNAL COMPONENT VALUES
INDUCTOR VALUE OPTIMIZATION
The required inductor value(s) for the best performance depends on the operating frequency, and the board
layout specifications. The listed values in this datasheet are based on the calculated parasitic values from
PhaseLink’s evaluation board design (Gerber file available upon request). These inductor values provide the user
with a starting point to determine the optimum inductor values. Additional fine-tuning may be required to
determine the optimal solution.
To assist with the inductor value optimization, PhaseLink has developed the “AFM Tuning Assistant” software.
You can download this software from PhaseLink’s web site (www.phaselink.com). The software consists of two
worksheets. The first worksheet (named L2) is used to fine-tune the ‘L2’ inductor value, and the second
worksheet (named L4) is used for fine tuning of the ‘L4’ (used in 4x AFMs only) inductor value.
For those designs using PhaseLink’s recommended board layout, you can use the “AFM Tuning Assistant” to
determine the optimum values for the required inductors. This software is developed based on the parasitic
information from PhaseLink’s board layout and can be used to determine the required inductor and parallel
capacitor (see LWB1 and Cstray parameters) values. For those employing a different board layout in their
design, we recommend to use the parasitic information of their board layout to calculate the optimized inductor
values. Please use the following fine tuning procedure:



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