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PLL502-00DI Datasheet(PDF) 1 Page - PhaseLink Corporation

Part # PLL502-00DI
Description  Multiplier VCXO IC Die for 12 to 25MHz Parallel Resonant Crystals
PDF  4 Pages
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Manufacturer  PLL [PhaseLink Corporation]
Direct Link  http://www.phaselink.com
Logo PLL - PhaseLink Corporation

PLL502-00DI Datasheet(HTML) 1 Page - PhaseLink Corporation

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PLL502-00
Multiplier VCXO IC Die for 12 to 25MHz Parallel Resonant Crystals
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/17/04 Page 1
FEATURES
• Integrated voltage-controlled crystal oscillator
circuitry (VCXO) (pull range 500ppm minimum).
• Low phase noise (-130dBc @ 10kHz offset at
44MHz output)
• Selectable frequency multipliers (x1, x2, x4, x8).
• 3.3V supply voltage.
• Uses inexpensive fundamental-mode parallel
resonant crystals (from 12 to 25MHz).
• Selectable High Drive (30mA) or Standard Drive
(10mA) output.
• Available in DIE (65 mil x 62 mil).
DESCRIPTION
The PLL502-00 is a monolithic low jitter and low
phase noise (-130dBc @10kHz offset at 44MHz
output), high performance CMOS VCXO IC Die, that
uses a low cost crystal (12-25MHz).
The same die can be used as a VCXO with output
frequencies ranging from FXIN x 1 to FXIN x 8 using
selector pad bonding options (see Multiplier
Selection Table on this page). This makes the
PLL502-00 ideal for a wide range of applications
from 12MHz to 190MHz (including 27MHz,
35.328MHz, 77.76MHz and 155.52MHz, etc.).
BLOCK DIAGRAM
DIE SPECIFICATIONS
Name
Value
Size
65 x 62 mil
Reverse side
GND
Pad dimensions
80 micron x 80 micron
Thickness
10 mil
DIE CONFIGURATION
MULTIPLIER SELECTION
SELECTION
S2
S1
S0
FXIN
CLK (MHz)
0
0
0
FXIN x 2
0
0
1
FXIN x 4
0
1
0
FXIN x 1
0
1
1
FXIN x 2*
1
0
0
FXIN x 8
1
0
1
FXIN x 1*
1
1
0
FXIN x 4*
1
1
1
12MHz – 25MHz
FXIN x 8*
Note: - Selector pads default to ‘0’, wire bond to VDD to set to ‘1’
- (*) High-drive output
PAD DESCRIPTION
Name
Number
Description
XIN
27
Crystal input connection.
XOUT
29
Crystal output connection.
VCON
31
Voltage Control Input.
GND
7,10
Ground.
CLK
13
Clock Output.
S[0:2]
18,19,20
Frequency selection pads
VDD
21,22,23
3.3V Power Supply.
OE
25
Output Enable: ‘0’ to disable (tri-state
output), 1’ (default value when not
connected) to enabled the output.
VCON
XIN
VCXO
CLK
Selectable
PLL
18
19
20
21
23
25
7
13
10
27
29
31
Y
X
(0,0)
(1550,1475)
65 mil
GND
CLK
VCON
XOUT
XIN
Die ID:
A0707-07A
C502A
Note:
^ denotes internal pull up
V denotes internal pull down


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