SLG46517 datasheet(2/190 Pages) DIALOG

2 / 190 page

Datasheet

22-Jul-2021

CFR0011-120-00

Revision 3.6

2 of 190

SLG46517

GreenPAK Programmable Mixed-Signal Matrix

with ASM and Dual 44 m

Ω/2 A P-FET

Contents

General Description .................................................................................................................................................................1

Key Features.............................................................................................................................................................................1

Applications..............................................................................................................................................................................1

1 Block Diagram ......................................................................................................................................................................9

2 Pinout ..................................................................................................................................................................................10

2.1 Pin Configuration - MSTQFN- 28L .......................................................................................................................10

3 Characteristics ...................................................................................................................................................................15

3.1 Absolute Maximum Ratings .................................................................................................................................15

3.2 Electrostatic Discharge Ratings ...........................................................................................................................15

3.3 Recommended Operating Conditions .................................................................................................................16

3.4 Electrical Characteristics ......................................................................................................................................16

3.5 Timing Characteristics ..........................................................................................................................................20

3.6 OSC Characteristics .............................................................................................................................................22

3.7 ACMP Characteristics ..........................................................................................................................................26

3.8 Power Switch EC (Each P-FET) ..........................................................................................................................30

4 User Programmability ........................................................................................................................................................32

5 IO Pins .................................................................................................................................................................................33

5.1 Input Modes .........................................................................................................................................................33

5.2 Output Modes .......................................................................................................................................................33

5.3 Pull-Up/Down Resistors .......................................................................................................................................34

5.4 IO Register Settings .............................................................................................................................................34

5.5 GPI Structure .......................................................................................................................................................41

5.6 Matrix OE IO Structure .........................................................................................................................................42

5.7 IO Structure ..........................................................................................................................................................45

6 Connection Matrix ..............................................................................................................................................................47

6.1 Matrix Input Table ...............................................................................................................................................48

6.2 Matrix Output Table ..............................................................................................................................................50

6.3 Connection Matrix Virtual Inputs ..........................................................................................................................53

6.4 Connection Matrix Virtual Outputs .......................................................................................................................53

7 Combination Function Macrocells ....................................................................................................................................54

7.1 2-Bit LUT or D Flip-Flop Macrocells .....................................................................................................................54

7.2 3-Bit LUT or D Flip-Flop with Set/Reset Macrocells .............................................................................................58

7.3 3-Bit LUT or Pipe Delay Macrocell .......................................................................................................................66

7.4 3-Bit LUT or 8-Bit Counter/Delay Macrocells .......................................................................................................68

7.5 4-Bit LUT or 16-Bit Counter/Delay Macrocells .....................................................................................................76

7.6 CNT/DLY/FSM Timing Diagrams .........................................................................................................................81

7.7 2-bit LUT or Programmable Pattern Generator ....................................................................................................88

7.8 Wake and Sleep Controller ..................................................................................................................................89

8 Analog Comparators ..........................................................................................................................................................93

8.1 ACMP0 Block Diagram and Register Settings .....................................................................................................96

8.2 ACMP1 Block Diagram and Register Settings .....................................................................................................98

8.3 ACMP2 Block Diagram and Register Settings ...................................................................................................100

8.4 ACMP3 Block Diagram and Register Settings ...................................................................................................102

9 Pipe Delay .........................................................................................................................................................................104

10 Programmable Delay/Edge Detector ............................................................................................................................104

10.1 Programmable Delay Timing Diagram - Edge Detector Output .......................................................................104

11 Additional Logic Function. Deglitch Filter ...................................................................................................................106

11.1 Deglitch Filter/Edge Detector ...........................................................................................................................106

12 Voltage Reference ..........................................................................................................................................................107

12.1 Voltage Reference Overview ...........................................................................................................................107

12.2 Vref Selection Table ........................................................................................................................................107

12.3 Vref Block Diagram ........................................................................................................................................108

12.4 Vref Load Regulation .......................................................................................................................................109

13 Clocking ..........................................................................................................................................................................111

13.1 OSC General Description .................................................................................................................................111

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