AC Characteristics

SYMBOL

PARAMETER

MIN

TYP

MAX

UNITS

VCO Frequency (see Note 1)

40

260

MHz

Crystal Frequency

5

20

MHz

Cpar

Crystal Oscillator Loading Capacitance

20

pf

LOAD Frequency

80

MHz

XTAL1 High Time (when driven externally)

8

ns

XTAL1 Low Time (when driven externally)

8

ns

PLL Acquire Time (to within 1%)

500

µs

VDD Supply Current

15

t.b.d.

mA

VDDO Supply Current (excluding CLK+/

−

termination)

20

t.b.d.

mA

Differential Clock Output Duty Cycle

(see Note 2)

45

55

%

Differential Clock Output Cumulative Jitter

(see Note 3)

<0.06

pixel

DIGITAL INPUTS - ICS1562B-001

1

Address Setup Time

10

ns

2

Address Hold Time

10

ns

3

Data Setup Time

10

ns

4

Data Hold Time

10

ns

5

ns

DIGITAL INPUTS - ICS1562B-201

6

DATA/HOLD~ Setup Time

10

ns

7

DATA/HOLD~ Hold Time

10

ns

8

ns

PIPELINE DELAY RESET

9

Reset Activation Time

2*Tclk

ns

10

Reset Duration

4*Tload

ns

11

Restart Delay

2*Tload

ns

12

Restart Matching

-1*Tclk

+1.5*Tclk

ns

DIGITAL OUTPUTS

13

CLK+/CLK

− Clock Rate

260

MHz

14

LOAD To LD/N2 Skew (Shift Clock Mode)

-2

0

+2

ns

Note 1: Use of the post-divider is required for frequencies lower than 40 MHz on CLK+ & CLK- outputs. Use of the post-divider

is recommended for output frequencies lower than 65 MHz.

Note 2: Using load circuit of Figure 6. Duty cycle measured at zero crossings of difference voltage between CLK+ and CLK-.

Note 3: Cumulative jitter is defined as the maximum error (in the domain) if any CLK edge, at any point in time, compared with

the equivalent edge generated by an ideal frequency source.

ICS laboratory testing indicates that the typical value shown above can be treated as a maximum jitter specification in

virtually all applications. Jitter performance can depend somewhat on circuit board layout, decoupling, and register

programming.

ICS1562B

17