SCIMX6DP7AYM2AB datasheet(53/168 Pages) NXP

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Electrical Characteristics

i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018

NXP Semiconductors

4.9

System Modules Timing

This section contains the timing and electrical parameters for the modules in each i.MX

6DualPlus/6QuadPlus processor.

4.9.1

Reset Timing Parameters

Figure 10 shows the reset timing and Table 38 lists the timing parameters.

Figure 10. Reset Timing Diagram

4.9.2

WDOG Reset Timing Parameters

Figure 11 shows the WDOG reset timing and Table 39 lists the timing parameters.

Figure 11. WDOG1_B Timing Diagram

NOTE

XTALOSC_RTC_XTALI is approximately 32 kHz.

XTALOSC_RTC_XTALI cycle is one period or approximately 30

μs.

NOTE

WDOG1_B output signals (for each one of the Watchdog modules) do not

have dedicated pins, but are muxed out through the IOMUX. See the IOMUX

manual for detailed information.

Table 38. Reset Timing Parameters

Parameter

Min

Max

Unit

CC1

Duration of SRC_POR_B to be qualified as valid

—

XTALOSC_RTC_ XTALI cycle

Table 39. WDOG1_B Timing Parameters

Parameter

Min

Max

Unit

CC3

Duration of WDOG1_B Assertion

—

XTALOSC_RTC_ XTALI cycle

SRC_POR_B

CC1

(Input)

WDOG1_B

CC3

(Output)

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