FDA036AST

www.futurewafer.com.tw

Document Number:F12126A

31-Mar-2021 V 2.0

Latch Up High Current ESD Protection Device

Electrical Characteristics

Fig .2 Clamping Voltage VC Map I/O Pins to Pin 2

Fig. 5 Power Derating Curve

Fig .4 Pulse Wave Form

Fig. 3 Normalized Capacitance vs.Reverse Voltage

Reverse Voltage VR,V

I/O-GND

I/O-I/O

Application Information

In applications where no positive supply reference is available, or complete supply isolation is desired, the

internal TVS may be used as the reference.In case, pin 5 is not connected. The steering diodes will begin to

conduct when the voltage on the protected line exceeds the working voltage of the TVS.

I/O 1

I/O 2

I/O 3

I/O 4

To Protected IC

To Protected IC

NC

GND

Data Line Protection Using Internal TVS diode as Reference

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t-Time (uS)

TEST WAVEFORM

PARAMETERS

tf=8us

td=20us

Td=t

PP/2