MPC8560 datasheet(6/108 Pages) NXP

6 / 108 page

MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2

Freescale Semiconductor

Overview

— Interrupts can be routed to the e500 core’s standard or critical interrupt inputs

— Interrupt summary registers allow fast identification of interrupt source

•I2C controller

— Two-wire interface

— Multiple master support

— Master or slave I2C mode support

— On-chip digital filtering rejects spikes on the bus

•

Boot sequencer

— Optionally loads configuration data from serial ROM at reset via the I2C interface

— Can be used to initialize configuration registers and/or memory

— Supports extended I2C addressing mode

— Data integrity checked with preamble signature and CRC

•

Local bus controller (LBC)

— Multiplexed 32-bit address and data operating at up to 166 MHz

— Eight chip selects support eight external slaves

— Up to eight-beat burst transfers

— The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller

— Three protocol engines available on a per chip select basis:

– General purpose chip select machine (GPCM)

– Three user programmable machines (UPMs)

– Dedicated single data rate SDRAM controller

— Parity support

— Default boot ROM chip select with configurable bus width (8-,16-, or 32-bit)

•

Two three-speed (10/100/1Gb) Ethernet controllers (TSECs)

— Dual IEEE 802.3, 802.3u, 802.3x, 802.3z, 802.3ac, 802.3ab compliant controllers

— Support for different Ethernet physical interfaces:

– 10/100/1Gb Mbps IEEE 802.3 GMII

– 10/100 Mbps IEEE 802.3 MII

– 10 Mbps IEEE 802.3 MII

– 1000 Mbps IEEE 802.3z TBI

– 10/100/1Gb Mbps RGMII/RTBI

— Full- and half-duplex support

— Buffer descriptors are backward compatible with MPC8260 and MPC860T 10/100

programming models

— 9.6-Kbyte jumbo frame support

— RMON statistics support

— 2-Kbyte internal transmit and receive FIFOs

MPC8560 Datasheet(PDF) 6 Page - NXP Semiconductors

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