MWPR1024IZVHT datasheet(8/86 Pages) NXP

8 / 86 page

• Flash implemented as two equal blocks each of 256 KB block. Code can

execute or read from one block while the other block is being erased or

programmed.

• Firmware distribution protection. Program flash can be marked execute-only

on a per-sector (8 KB) basis to prevent firmware contents from being read by

third parties.

• 128 KB SRAM

• Security circuitry to prevent unauthorized access to RAM and flash contents

through the debugger

3.4 System features

Power Management Control Unit (PMC)

• Programmable power saving modes

• Available wake-up from power saving modes via internal and external sources

• Integrated Power-on Reset (POR)

• Integrated Low Voltage Detect (LVD) with reset (brownout) capability

• Selectable LVD trip points

• Programmable Low Voltage Warning (LVW) interrupt capability

• Individual peripheral clocks can be gated off to reduce current consumption

• Internal Buffered bandgap reference voltage

• Factory programmed trim for bandgap and LVD

• 1 kHz Low Power Oscillator (LPO)

DC-DC Converters

• Internal switched mode power supply supporting Buck, Boost, and Bypass

operating modes

• Buck operation supports external voltage sources of 2.1 V to 4.2 V. This reduces

peak current consumption during Rx and Tx by ~25%, ideal for single coin-cell

battery operation (typical CR2032 cell).

• Boost operation supports external voltage sources of 0.9 V to 1.795 V, which is

efficiently increased to the static internal core voltage level, ideal for single battery

operation (typical AA or AAA alkaline cell).

• When DC-DC is not used, the device supports an external voltage range of 1.5 V to

3.6 V (1.5 - 3.6 V on VDD_RF1, VDD_RF2, VDD_XTAL and

VDD_1P5OUT_PMCIN pins. 1.71 - 3.6 V on VDD_0, VDD_1 and VDDA pins)

Feature Descriptions

MWPR1124ZVHT/MWPR1024IZVHT Data Sheet, Rev. 0, 04/2018

NXP Semiconductors

MWPR1024IZVHT Datasheet(PDF) 8 Page - NXP Semiconductors