11 Layout

11.1 Layout Guidelines

• Connect ANODE, GATE and CATHODE pins of LM74700-EP close to the MOSFET's SOURCE, GATE and

DRAIN pins.

• The high current path for this solution is through the MOSFET. Therefore, it is important to use thick traces for

source and drain of the MOSFET to minimize resistive losses.

• The charge pump capacitor across VCAP and ANODE pins must be kept away from the MOSFET to lower

the thermal effects on the capacitance value.

• The Gate pin of the LM74700-EP must be connected to the MOSFET gate with short trace. Avoid excessively

thin and long trace to the Gate Drive.

• Keep the GATE pin close to the MOSFET to avoid increase in MOSFET turn-off delay due to trace

resistance.

• Obtaining acceptable performance with alternate layout schemes is possible. However, the layout shown in

Figure 11-1 is intended as a guideline.

11.2 Layout Example

VOUT

GND PLANE

VIN

Signal Via

Power Via

Top layer

MOSFET DRAIN

MOSFET SOURCE

Figure 11-1. LM74700-EP DDF Package Layout Example

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LM74700-EP

SNOSDD6 – SEPTEMBER 2021

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Product Folder Links: LM74700-EP