ML7055LP datasheet(19/30 Pages) OKI

19 / 30 page

FEDL7055-02

OKI Semiconductor

ML7055

19/30

PCM interface

(Vdd = 2.7 to 3.6V, CoreVdd = 1.65 to 1.95V, Ta = -40 to 85°C)

Parameter

Description

Min

Typ

Max

Unit

Tpc0

PCMIN setup time relative to PCMCLK (input) falling edge

100

—

Tpc1

PCMIN hold time relative to PCMCLK (input) falling edge

100

—

Tpc2

PCMOUT delay time relative to PCMCLK (input) rising edge

—

250

Tpc3

PCMSYNC (input) setup time relative to PCMCLK (input)

rising edge

100

—

Tpc4

PCMSYNC (input) hold time relative to PCMCLK (input)

rising edge

100

—

Tpc5

PCMIN setup time relative to PCMCLK (output) falling edge

100

—

Tpc6

PCMIN hold time relative to PCMCLK (output) falling edge

100

—

Tpc7

PCMOUT delay time relative to PCMCLK (output) rising

edge

—

250

Tpc8

Delay time from PCMCLK (output) rising edge to PCMSYNC

(output)

—

150

AC Characteristic Measuring Points

VDD

0 V

0.8VDD

0.2VDD

0.8VDD

0.2VDD

PCMCLK(I)

PCMIN

PCMOUT

Tpc2

Tpc0

Tpc1

PCMSYNC(I)

Tpc3

Tpc4

Tpc3

Tpc4

PCMCLK(O)

PCMIN

PCMOUT

Tpc5

Tpc6

PCMSYNC(O)

Tpc 8

Tpc7

Tpc 7

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