TCS3471 datasheet(21/38 Pages) AMSCO

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ams Datasheet

Page 21

[v1-01] 2018-Mar-27

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TCS3471 − Register Description

RGBC Timing Register (0x01)

The RGBC timing register controls the internal integration time

of the RGBC clear and IR channel ADCs in 2.4 ms increments.

Max RGBC Count = (256 - ATIME) × 1024 up to a maximum of

65535.

Figure 25:

RGBC Timing Register

Wait Time Register (0x03)

Wait time is set 2.4 ms increments unless the WLONG bit is

asserted, in which case the wait times are 12x longer. WTIME is

programmed as a 2’s complement number.

Figure 26:

Wait Time Register

Field

Bits

Description

ATIME

7:0

VALUE

INTEG_CYCLES

TIME

MAX COUNT

0xFF

2.4 ms

1024

0xF6

24 ms

10240

0xD5

101 ms

43008

0xC0

154 ms

65535

0x00

256

700 ms

65535

Field

Bits

Description

WTIME

7:0

VALUE

WAIT TIME

TIME (WLONG = 0)

TIME (WLONG = 1)

0xFF

2.4 ms

0.029 s

0xAB

204 ms

2.45 s

0x00

256

614 ms

7.4 s

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