ES9219C datasheet(51/67 Pages) ESS

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ES9219 Datasheet

CONFIDENTIAL ADVANCE INFORMATION 1.0.4

February 27, 2020

ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA Tel (408) 643-8800 • Fax (408) 643-8801

Read-Only Registers

I2C Slave Access:

I2S Sync Slave Access:

Clock Domain:

Bits

[7:2]

[1]

[0]

Mnemonic

CHIP_ID

AUTOMUTE _STATUS

LOCK_STATUS

Bits

Mnemonic

Description

[7:2]

CHIP_ID

6’b100011: ES9219

[1]

AUTOMUTE _STATUS

Indicator for when automute has become active.

1’b0: automute condition is inactive

1’b1: automute condition has been flagged and is active

[0]

LOCK_STATUS

Indicator for when DPLL is locked (when in slave mode) or 1’b1 when the ES9219 is the master.

1’b0: DPLL is not locked to the incoming audio sample rate (which could mean that no audio input is

present, the lock has not completed, or the ES9219 is unable to lock due to clock jitter or drift)

1’b1: DPLL is locked to the incoming audio sample rate, or the ES9219 is in master or 128*fs mode

I2C Slave Access:

I2S Sync Slave Access:

Clock Domain:

Bits

[7]

[6]

[5]

[4]

[3:2]

[1]

[0]

Mnemonic

ocbr_pos

ocbl_pos

ocbr_neg

obcl_neg

clk_gear_rb

gpio2

gpio1

Bits

Mnemonic

Description

[7]

ocbr_pos

Indicates instantaneous positive overcurrent condition on the right channel.

1’b0 No positive overcurrent condition (default)

1’b1 Positive overcurrent condition at the amplifier output

[6]

ocbl_pos

Indicates instantaneous positive overcurrent condition on the left channel.

1’b0 No positive overcurrent condition (default)

1’b1 Positive overcurrent condition at the amplifier output

[5]

ocbr_neg

Indicates instantaneous negative overcurrent condition on the right channel

1’b0 No negative overcurrent condition (default)

1’b1 Negative overcurrent condition at the amplifier output

[4]

obcl_neg

Indicates instantaneous negative overcurrent condition on the right channel

1’b0 No negative overcurrent condition (default)

1’b1 Negative overcurrent condition at the amplifier output

[3:2]

clk_gear_rb

Clock gear readback. This register will reflect changes from both manual and automatic clock gearing

2’b00: indicates CLK = XI(MCLK) (default)

2’b01: indicates CLK = XI(MCLK) / 2

2’b10: indicates CLK = XI(MCLK) / 4

2’b11: indicates CLK = XI(MCLK) / 8

[1]

gpio2

Contains the state of the GPIO2 pin

[0]

gpio1

Contains the state of the GPIO1 pin

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