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HT46R14 Datasheet(PDF) 13 Page - Holtek Semiconductor Inc |
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HT46R14 Datasheet(HTML) 13 Page - Holtek Semiconductor Inc |
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13 / 47 page  HT46R14 Rev. 1.00 13 November 1, 2005 An extra option load time delay is added during system reset (power-up, WDT time-out at normal mode or RES reset). Program Counter 000H Interrupt Disable Prescaler, Divider Cleared WDT Clear. After master reset, WDT begins counting Timer/Event Counter Off PPG Timer Off PPG output Floating Input/Output Ports Input mode Stack Pointer Points to the top of the stack The registers states are summarized in the following table. Register Reset (Power On) WDT Time-out (Normal Operation) RES Reset (Normal Operation) RES Reset (HALT) WDT Time-out (HALT)* MP0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu MP1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu Program Counter 000H 000H 000H 000H 000H TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu STATUS --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu INTC0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu TMR0 xxxx xxxx xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TMR0C 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu TMR1 xxxx xxxx xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TMR1C 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u--- PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PB 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PBC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PC ---- 1111 ---- 1111 ---- 1111 ---- 1111 ---- uuuu PCC ---- 1111 ---- 1111 ---- 1111 ---- 1111 ---- uuuu INTC1 -000 -000 -000 -000 -000 -000 -000 -000 -uuu -uuu PPG0C 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu PPGT0 xxxx xxxx xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu PPG1C 0000 00-0 0000 00-0 0000 00-0 0000 00-0 uuuu uu-u PPGT1 xxxx xxxx xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu ADRL x--- ---- x--- ---- x--- ---- x--- ---- u--- ---- ADRH xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ADCR 0100 0000 0100 0000 0100 0000 0100 0000 uuuu uuuu ACSR ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu Note: ²*² stands for ²warm reset² ²u² stands for ²unchanged² ²x² stands for ²unknown² |
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