HT46R14 datasheet(21/47 Pages) HOLTEK

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HT46R14

Rev. 1.00

November 1, 2005

Input/Output Ports

There are 20 bidirectional input/output lines in the

microcontroller, labeled as PA, PB, PC, which are mapped

to the data memory of [12H], [14H] and [16H] respectively.

All of these I/O ports can be used for input and output op-

erations. For input operation, these ports are

non-latching, that is, the inputs must be ready at the T2

rising edge of instruction

²MOV A,[m]² (m=12H, 14H or

16H). For output operation, all the data is latched and re-

mains unchanged until the output latch is rewritten.

Each I/O line has its own control register (PAC, PBC,

PCC) to control the input/output configuration. With this

control register, CMOS output or Schmitt trigger input with

or without pull-high resistor structures can be reconfig-

ured dynamically under software control. To function as an

input, the corresponding latch of the control register must

write

²1². The input source also depends on the control

²1², the input will read

the pad state. If the control register bit is

²0², the contents

of the latches will move to the internal bus. The latter is

possible in the

²read-modify-write² instruction.

For output function, CMOS is the only configuration.

These control registers are mapped to locations 13H, 15H

and 17H.

After a chip reset, these input/output lines remain at high

levels or floating state (depending on pull-high options).

Each bit of these input/output latches can be set or

cleared by

²SET [m].i² and ²CLR [m].i² (m=12H, 14H or

16H) instructions.

Some instructions first input data and then follow the out-

put operations. For example,

²SET [m].i², ²CLR [m].i²,

²CPL [m]², ²CPLA [m]² read the entire port states into the

CPU, execute the defined operations (bit-operation), and

then write the results back to the latches or the accumula-

tor.

Each line of port A has the capability of waking-up the de-

vice. Each I/O port has a pull-high option. Once the

pull-high option is selected, the I/O port has a pull-high re-

sistor, otherwise, there

¢s none. Take note that a

non-pull-high I/O port operating in input mode will cause a

floating state.

The PA0, PA3, PA4, PA5, PA6 and PA7 are pin-shared

with PPG1, PFD, TMR0, INT0, INT1 and TMR1 pins re-

spectively. And the PC0, PC1, PC2 and PC3 are

pin-shared with C0VIN1-, C0VIN+, C0OUT, C1OUT.

The PA3 is pin-shared with the PFD signal. If the PFD op-

tion is selected, the output signal in output mode of PA3

will be the PFD signal generated by the timer/event coun-

ter overflow signal. The input mode always remain in its

original functions. Once the PFD option is selected, the

PFD output signal is controlled by PA3 data register only.

Writing a

²1² to PA3 data register will enable the PFD out-

put function and writing

²0² will force the PA3 to remain at

²0².

V D D

E N

( P F D )

O P 0 ~ O P 7

I N T 0 f o r P A 5 O n l y

I N T 1 f o r P A 6 O n l y

T M R 0 f o r P A 4 O n l y

T M R 1 f o r P A 7 O n l y

S y s t e m W a k e - u p ( P A o n l y )

R e a d D a t a R e g i s t e r

C K

C o n t r o l B i t

P U

D a t a B u s

W r i t e C o n t r o l R e g i s t e r

C h i p R e s e t

R e a d C o n t r o l R e g i s t e r

W r i t e D a t a R e g i s t e r

D a t a B i t

P A 0 / P P G 1

P A 1 , P A 2

P A 3 / P F D

P A 4 / T M R 0

P A 5 / I N T 0

P A 6 / I N T 1

P A 7 / T M R 1

P B 0 / A N 0 ~ P B 7 / A N 7

P C 0 / C 1 V I N -

P C 1 / C 1 V I N +

P C 2 / C 1 O U T

P C 3 / C 2 O U T

( P A 0 ) P A 3

( P P G 1 ) P F D

Input/Output Ports

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