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4.15 Communication Timing

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units

Comments

SCL clock frequency

0

-

1000

kHz

Hold time (repeated)

START condition

After this period, the first

clock pulse is generated

0.24

-

-

µs

LOW period of the SCL

clock

0.53

-

-

µs

HIGH period of the SCL

clock

0.26

-

-

µs

SDA hold time

0

-

250

ns

Transmitting data

0

-

- -

ns

Receiving data

SDA set-up time

100

-

-

ns

SCL/SDA rise time

-

-

300

ns

SCL/SDA fall time

-

-

300

ns

SDA valid time

-

-

0.9

µs

Set-up time for a repeated

START condition

0.26

-

-

µs

Set-up time for STOP

condition

0.26

-

-

µs

Capacitive load on bus line

CB

-

-

400

pF

Low level input voltage

0

-

V

High level input voltage

-

V

Low level output voltage

33 mA sink current

-

-

0.4

V

Table 20: Timing specifications for I2C communication, valid for T=-40°C … 125°C and VDD = VDDmin… VDDmax. The

nomenclature above is according to the I2C Specification (UM10204, Rev. 6, April 4, 2014).

Figure 5: Timing diagram for digital input/output pads. SDA directions are seen from the sensor. Bold SDA lines are controlled

by the sensor, plain SDA lines are controlled by the micro-controller. Note that SDA valid read time is triggered by falling edge

of preceding toggle.

SCL

70%

30%

SDA

70%

30%

DATA IN

SDA

70%

30%

DATA OUT