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LTM4650A Datasheet(PDF) 20 Page - Analog Devices

Part # LTM4650A
Description  Quad DC/DC 關Module Regulator with Configurable Dual 12A, Dual 5A Output Array
PDF  36 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

LTM4650A Datasheet(HTML) 20 Page - Analog Devices

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LTM4671
20
Rev. B
For more information www.analog.com
Figure 6. Output Coincident Tracking Waveform
4671 F06
TIME
VOUT0 = 1.0V
VOUT3 = 1.2V
VOUT2 = 2.5V
VOUT1 = 3.3V
RFB(SL)
RFB(SL) + 60.4k
=
RTR(BOT)
RTR(TOP) + RTR(BOT)
From the equation, we could easily find out that, in the
coincident tracking, the slave regulator’s TRACK/SS pin
resistor divider is always the same as its feedback divider.
For example, RTR(TOP)3 = 60.4k and RTR(BOT)3 = 60.4k
is  a good combination for coincident tracking for
VOUT(MA) = 3.3V and VOUT(SL) =1.2V application.
POWER GOOD
The PGOOD pins are open-drain pins that can be used to
monitor valid output voltage regulation. This pin monitors
a ±10% window around the regulation point. A resistor
can be pulled up to a particular supply voltage for moni-
toring. To prevent unwanted PGOOD glitches during tran-
sients or dynamic VOUT changes, the LTM4671’s PGOOD
falling edge includes a blanking delay of approximately
52 switching cycles.
STABILITY COMPENSATION
The LTM4671 module internal compensation loop of each
regulator channel is designed and optimized for low ESR
ceramic output capacitors only application (COMPb tied
to COMPa for 12A channels). Table 3 is provided for most
application requirements using the optimized internal
compensation. In case of all ceramic output capacitors
is required for output ripples or dynamic transient spike
reduction, an additional 10pF to 15pF phase boost cap is
required between VOUT and FB pins.
For specific optimized requirement for the dual 12A chan-
nels, disconnect COMPb from COMPa and apply a Type II
C-R-C compensation network from COMPa to SGND to
achieve external compensation.
The LTpowerCAD design tool is available to download
online to perform specific control loop optimization and
analyzethecontrolstabilityandloadtransientperformance.
RUN ENABLE
Pulling the RUN pin of each regulator channel to ground
forcestheregulatorintoitsshutdownstate,turningoffboth
power MOSFETs and most of its internal control circuitry.
Bringing the RUN pin above 0.7V turns on the internal
reference only, while still keeping the power MOSFETs
off. Further increasing the RUN pin voltage above 1.2V
will turn on the entire regulator channel.
TEMPERATURE MONITORING
The 12A Channels (CH0, CH3):
Measuring the absolute temperature of a diode is pos-
sible due to the relationship between current, voltage
and temperature described by the classic diode equation:
ID = IS •e
VD
η • VT
⎛
⎝⎜
⎞
⎠⎟
or
VD = η • VT •In
ID
IS
where ID is the diode current, VD is the diode voltage, η
is the ideality factor (typically close to 1.0) and IS (satu-
ration current) is a process dependent parameter. VT can
be broken out to:
VT =
k • T
q
APPLICATIONS INFORMATION



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