LTM4650A datasheet(23/36 Pages) AD

23 / 36 page

LTM4671

Rev. B

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A graphical representation of the aforementioned ther-

mal resistances is given in Figure 9; blue resistances are

contained within the μModule regulator, whereas green

resistances are external to the µModule.

As a practical matter, it should be clear to the reader that

no individual or sub-group of the four thermal resistance

parameters defined by JESD51-12 or provided in the Pin

Configuration section replicates or conveys normal op-

erating conditions of a μModule. For example, in normal

board-mounted applications, never does 100% of the

device’s total power loss (heat) thermally conduct exclu-

sively through the top or exclusively through bottom of the

µModule—asthestandarddefinesforθJCtopandθJCbottom,

respectively.Inpractice,powerlossisthermallydissipated

in both directions away from the package—granted, in the

absence of a heat sink and airflow, a majority of the heat

flow is into the board.

Within a SIP (system-in-package) module, be aware there

are multiple power devices and components dissipating

power, with a consequence that the thermal resistances

relative to different junctions of components or die are not

exactly linear with respect to total package power loss. To

reconcile this complication without sacrificing modeling

simplicity—but also, not ignoring practical realities—an

approach has been taken using FEA software modeling

along with laboratory testing in a controlled-environment

chamber to reasonably define and correlate the thermal

resistance values supplied in this data sheet: (1) Initially,

FEA software is used to accurately build the mechanical

geometry of the µModule and the specified PCB with all of

thecorrectmaterialcoefficientsalongwithaccuratepower

losssourcedefinitions;(2)thismodelsimulatesasoftware-

defined JEDEC environment consistent with JSED 51-9 to

predict power loss heat flow and temperature readings

at different interfaces that enable the calculation of the

JEDEC-defined thermal resistance values; (3) the model

and FEA software is used to evaluate the µModule with

heat sink and airflow; (4) having solved for and analyzed

these thermal resistance values and simulated various

operating conditions in the software model, a thorough

laboratory evaluation replicates the simulated conditions

with thermocouples within a controlled-environment

chamber while operating the device at the same power

loss as that which was simulated. An outcome of this

process and due-diligence yields a set of derating curves

provided in other sections of this data sheet. After these

laboratory tests have been performed and correlated to

the µModule model, then the θJB and θBA are summed

together to correlate quite well with the µModule model

withnoairfloworheatsinkinginaproperlydefinechamber.

This θJB + θBA value is shown in the Pin Configuration

section and should accurately equal the θJA value because

approximately 100% of power loss flows from the junc-

tion through the board into ambient with no airflow or top

mounted heat sink.

APPLICATIONS INFORMATION

Figure 9. Graphical Representation of JESD51-12 Thermal Coefficients

4671 F09

µModule DEVICE

JUNCTION-TO-CASE (TOP)

RESISTANCE

JUNCTION-TO-BOARD RESISTANCE

JUNCTION-TO-AMBIENT RESISTANCE (JESD51-9 DEFINED BOARD)

CASE (TOP)-TO-AMBIENT

RESISTANCE

BOARD-TO-AMBIENT

RESISTANCE

JUNCTION-TO-CASE

(BOTTOM) RESISTANCE

JUNCTION

AMBIENT

CASE (BOTTOM)-TO-BOARD

RESISTANCE

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