EM78P468LBQ datasheet(21/83 Pages) EMC

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EM78P468L

8-BIT Microcontroller

Product Specification (V1.0) 03.15.2006

• 17

(This specification is subject to change without further notice)

CNT1EN = “1” :

Enable Counter 1. Count operation start.

4.1.14

RD/SBPCR (System, Booster and PLL Control Register)

(Address: 0Dh)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CLK2

CLK1

CLK0

IDLE

BF1

BF0

CPUS

Bit 7:

Not used

Bit 6 ~ 4 (CLK2 ~ CLK0):

main clock selection bits for PLL mode (code option select)

CLK2

CLK1

CLK0

Main clock

Example Fs=32.768K

Fs*130

4.26 MHz

Fs*65

2.13 MHz

Fs*65/2

1.065 MHz

Fs*65/4

532 KHz

Fs*244

8 MHz

Bit 3 (IDLE) :

idle mode enable bit. This bit will decide the intended mode of the SLEP

instruction.

IDLE=”0”+SLEP instruction => sleep mode

IDLE=”1”+SLEP instruction => idle mode

* NOP instruction must be added after SLEP instruction.

Example : IDLE mode : IDLE bit = “1” +SLEP instruction + NOP instruction

SLEEP mode : IDLE bit = “0” +SLEP instruction + NOP instruction

Bit 2,1 (BF1, 0): LCD booster frequency select bit to adjust VLCD 2,3 driving.

BF1

BF0

Booster frequency

Fs/4

Fs/8

Fs/16

Bit 0 (CPUS):

CPU oscillator source select, When CPUS=0, the CPU oscillator select

sub-oscillator and the main oscillator is stopped.

CPUS = “0”:

sub-oscillator (Fs)

CPUS = “1”:

main oscillator (Fm)

EM78P468LBQ Datasheet(PDF) 21 Page - ELAN Microelectronics Corp

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