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WM8580 Datasheet(PDF) 25 Page - Wolfson Microelectronics plc |
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WM8580 Datasheet(HTML) 25 Page - Wolfson Microelectronics plc |
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25 / 92 page ![]() Product Preview WM8580 w PP Rev 1.0 March 2006 25 DSP MODE A In DSP Mode A, the MSB of Channel 1 left data is sampled on the second rising edge of BCLK following a LRCLK rising edge. Channel 1 right data then follows. For the PAIF Receiver, Channels 2 and 3 follow as shown in Figure 17. Figure 17 DSP Mode A Timing Diagram – PAIF Receiver Input Data For the SAIF receiver, only stereo information is processed. Figure 18 DSP Mode A Timing Diagram - SAIF Receiver Input Data The MSB of the left channel of the output data changes on the first falling edge of BCLK following a low to high LRCLK transition and may be sampled on the rising edge of BCLK. The right channel data is contiguous with the left channel data. Figure 19 DSP Mode A Timing Diagram – PAIF/SAIF Transmitter Data |
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