© VITESSE SEMICONDUCTOR CORPORATION

Page 1

11/9/99

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

VSC8131

2.488 Gbit/sec

32:1 SONET/SDH Mux with Clock Generator

G52249-0, Rev. 3.0

Features

General Description

The VSC8131 multiplexes 32 TTL compatible 77.76Mb/s Parallel Data Inputs (D0-D31) into a single

LVPECL 2.488 Gb/s serial output (DO+) for use in SONET STS-48/SDH STM-16 systems. An integrated

LVPECL compliant 77.76MHz reference clock (REFCLK+) which is

used to retime the transmitted serialized data.

A Divide-by-32 TTL clock output (CK78OUT) is used as a clock input (CK78IN) for timing of the parallel data

inputs. Parity Checking (PARBIT) is performed on the incoming data with a selectable even or odd TTL parity mode

input (PARMODE) and a TTL Parity Error (PARERR) output. A TTL Loss Of Lock (LOL) output indicator is used to

report the loss of the REFCLK+ or for conditions resulting in the CMU losing lock to incoming clock.

VSC8131 Block DIagram

• 2.488Gb/s 32:1 Mux with Clock Generator

• SONET STS-48/SDH STM-16

• LVPECL Differential High Speed Serial Data

and Clock Outputs

• 32 TTL Parallel Data Inputs with Odd/Even

Parity Check

• 128 Pin, 14x20x2 mm Enhanced-PQFP

• Single 3.3V Supply

• 2.15W Max Power Dissipation

32:1

Multiplexer

Output

Register

PARBIT

D0

D31

Bit Rate Clock

Parallel Data

Receivers

Input

Registers

Timing

Generator

Clock/32

CMU

x32

LOL

CO+

CO-

DO+

DO-

CK78OUT

PARMODE

CK78IN

Parity

Register

PARERR

REFCLK+

REFCLK-