UCD7100APWPR datasheet(16/30 Pages) TI

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10.2.2 Detailed Design Procedure

The cycle-by-cycle current protection is implemented by connecting the current sense signal to the CS pin.

When the CS level is greater than the ILIM voltage minus 25 mV, the output of the driver is forced low and the

current limit flag (CLF) is set high. The CLF signal is latched high until the UCD7K device receives the next rising

edge on the IN pin.

(6)

(7)

The current limit threshold can be set to any value between 0.25 V and 1.0 V, so Rsense must be between 0.045

Ω and 0.195 Ω. For example, if Rsense is 0.15 Ω, then VILIM must be 0.775 V to protect input current at 5 A. If

the digital controller has an internal digital-to-analog converter, then it can generate 0.775 V and connect to ILIM

directly. For a digital controller without an internal digital-to-analog converter, it can generate a PWM signal, send

the PWM signal through a low pass filter, then connect to the ILIM pin. Assuming the magnitude of the PWM

pulse is 3.3 V, then the duty cycle is:

(8)

10.2.3 Application Curve

t − Time − 40 ns/div

Figure 10-2. Output Rise and Fall Time (VDD = 12 V, CLOAD = 10 NF)

UCD7100

SLUS651E – MARCH 2005 – REVISED NOVEMBER 2021

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UCD7100APWPR Datasheet(PDF) 16 Page - Texas Instruments