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ADAQ23876BBCZ Datasheet(PDF) 6 Page - Analog Devices |
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ADAQ23876BBCZ Datasheet(HTML) 6 Page - Analog Devices |
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6 / 37 page ![]() Data Sheet ADAQ23876 SPECIFICATIONS analog.com Rev. 0 | 6 of 37 Table 1. Parameter Test Conditions/Comments Min Typ Max Unit1 POWER REQUIREMENTS VDD 4.75 5 5.25 V VS+ 3 5 VS− + 10 V VS− VS+ − 10 0 +0.1 V VIO 2.375 2.5 2.625 V Total Standby Current12, 13 Static, all devices enabled 45 52 mA Static, all devices disabled 0.1 0.4 µA ADAQ23876 Current Draw VDD 4.6 5.5 mA VS+/VS− 4 5.5 mA VIO 40 42 mA ADAQ23876 Power Dissipation VDD = 5 V, VS+ = 5 V, VS− = 0 V VDD 19 26.25 mW VS+/VS− Gain = 0.37 24 28.875 mW VIO One-lane mode14 100 110.25 mW Total 143 165.375 mW TEMPERATURE RANGE Specified Performance TMIN to TMAX −40 +85 °C 1 The LSB unit means least significant bit. The weight of the LSB, referred to input, changes depending on the input voltage range. 2 For accurate resistor iPassive value IN2±, gain resistor (RG) = 1.5714286 3 The differential input ranges, VIN, must be within the allowed input common-mode range as per Figure 60 to Figure 64. VIN is dependent on the VS+/VS− supply rails used. 4 The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADAQ23876 running at a throughput rate of 15 MSPS. 5 fS = 15 MHz, and the REFBUF current (IREFBUF) varies linearly with the throughput rate. 6 Transient response is the time required for the ADAQ23876 to acquire a full-scale input step to within ±1 LSB accuracy. Guaranteed by design, not subject to test. 7 See the 1/f noise plot in Figure 65 8 All ac specifications expressed in decibels are referenced to the full-scale input range (FSR) and are tested with an input signal at 1 dB below full scale, unless otherwise specified. 9 Guaranteed by design, not subject to test. 10 When REFBUF is overdriven, turn off the internal reference buffer by setting REFIN = 0 V. Refer to the Voltage Reference Input section for more information. 11 The VCMO voltage can be used for other circuitry. However, drive the voltage with a buffer to ensure the VCMO voltage remains stable as per the specified range. 12 With all digital inputs forced to VIO or GND, as required. 13 During the acquisition phase. 14 In two-lane mode, the VIO power dissipation is about 10 mW higher than one-lane mode. |
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