P5/14

Rev. M, Aug 2012

ML1001

ii) Oscillator

a) Internal clock

The internal logic and the LCD driving signal of ML1001 are clocked either by the built-in oscillator or

from an external clock. When the internal oscillator is used, OEN should be connected to GND and the

OOUT should be connected to FIN. The oscillator will oscillate at 32 kHz and the frequency is

b) External clock

When using an external clock, the OEN is connected to VDD then connects the external clock to FIN.

iii) Timing

ML1001 have several frequencies of clock signal for the users to choose for the LCD display clock (ie.

LCLK) and the blink clock (ie. BCLK). They include the following clock signals :

Frequency of Clock Signal at FIN = 32 kHz

Actual Divider of FIN

Target Input Pin

2 KHz

1/16

LCLK

1 KHz

1/32

500 Hz

1/64

256 Hz

1/128

128 Hz

1/256

4 Hz

1/8192

BCLK

2 Hz

1/16384

1 Hz

1/32768

iv) Segment outputs

ML1001 has 40 segment outputs which should be connected directly to the LCD. If less than 40 segments

are required, the unused segments should be left open circuit. Users can disable the first 1 to 16 segments

and the last 17 to 40 segments by connecting the SEN1 and SEN2 to VDD, respectively. The segment

outputs shall output GND level after disabling it.

v) Common outputs

ML1001 consists of 2 common signals (ie. COM1A & COM1B). These two common signals are the

inversion of the LCLK. The common outputs should be left open-circuit if the outputs are unused. Users

can disable the COM1A and COM1B by connecting the CEN1A and CEN1B to VDD, respectively. The

common outputs will change to GND after disabling it.

vi) Blink

ML1001 has a blink function that users shall connect the BEN to GND and input the blink clock (ie.

BCLK) either by connecting ML1001 output clock signal from Frequency Divider or an external clock

signal. Users shall disable blink function by connecting BEN to VDD.