STM32F051X4 datasheet(51/122 Pages) STMICROELECTRONICS

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STM32F051x4 STM32F051x6 STM32F051x8

Electrical characteristics

IDD

Supply

current in

Sleep

mode

HSE

bypass,

PLL on

48 MHz 14.0 15.3(2)

15.3

16.0(2)

2.8

3.0(2)

3.0

3.2(2)

32 MHz 9.5

10.2

10.7

2.0

2.1

2.3

24 MHz 7.3

7.8

8.3

1.5

1.7

1.9

HSE

bypass,

PLL off

8 MHz

2.6

2.9

3.0

0.6

0.8

1 MHz

0.4

0.6

0.2

0.4

HSI clock,

PLL on

48 MHz 14.0

15.3

16.0

3.8

4.0

4.1

4.2

32 MHz 9.5

10.2

10.7

2.6

2.7

2.8

24 MHz 7.3

7.8

8.3

2.0

2.1

HSI clock,

PLL off

8 MHz

2.6

2.9

3.0

0.6

0.8

1. Data based on characterization results, not tested in production unless otherwise specified.

2. Data based on characterization results and tested in production (using one common test limit for sum of IDD and IDDA).

Table 25. Typical and maximum current consumption from VDD at 3.6 V (continued)

Symbol Parameter Conditions

fHCLK

All peripherals enabled

All peripherals disabled

Unit

Typ

Max @ TA

(1)

Typ

Max @ TA

(1)

25 °C

85 °C

105 °C

25 °C

85 °C

105 °C

Table 26. Typical and maximum current consumption from the VDDA supply

Symbol Parameter

Conditions

(1)

fHCLK

VDDA = 2.4 V

VDDA = 3.6 V

Unit

Typ

Max @ TA

(2)

Typ

Max @ TA

(2)

25 °C

85 °C

105 °C

25 °C

85 °C

105 °C

IDDA

Supply

current in

Run or

Sleep

mode,

code

executing

from Flash

memory or

RAM

HSE

bypass,

PLL on

48 MHz

150

170(3)

178

182(3)

164

183(3)

195

198(3)

µA

32 MHz

104

121

126

128

113

129

135

138

24 MHz

100

103

102

106

108

HSE

bypass,

PLL off

8 MHz

2.0

2.7

3.1

3.3

3.5

3.8

4.1

4.4

1 MHz

2.0

2.7

3.1

3.3

3.5

3.8

4.1

4.4

HSI clock,

PLL on

48 MHz

220

240

248

252

244

263

275

278

32 MHz

174

191

196

198

193

209

215

218

24 MHz

152

167

173

174

168

183

190

192

HSI clock,

PLL off

8 MHz

83.5

1. Current consumption from the VDDA supply is independent of whether the digital peripherals are enabled or disabled, being

in Run or Sleep mode or executing from Flash memory or RAM. Furthermore, when the PLL is off, IDDA is independent of

clock frequencies.

2. Data based on characterization results, not tested in production unless otherwise specified.

3. Data based on characterization results and tested in production (using one common test limit for sum of IDD and IDDA).

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