STM32L100RC datasheet(85/106 Pages) STMICROELECTRONICS

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STM32L100RC

I2S characteristics

Note:

Refer to the I2S section of the product reference manual for more details about the sampling

frequency (Fs), fMCK, fCK and DCK values. These values reflect only the digital peripheral

behavior, source clock precision might slightly change them. DCK depends mainly on the

ODD bit value, digital contribution leads to a min of (I2SDIV/(2*I2SDIV+ODD) and a max of

(I2SDIV+ODD)/(2*I2SDIV+ODD). Fs max is supported for each mode/condition.

1. Guaranteed by design.

2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB

Specification - Chapter 7 (version 2.0).

Table 52. I2S characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

fMCK

I2S Main Clock Output

256 x 8K 256xFs (1)

1. The maximum for 256xFs is 8 MHz

MHz

fCK

I2S clock frequency

Master data: 32 bits

64xFs

MHz

Slave data: 32 bits

64xFs

DCK

I2S clock frequency duty cycle Slave receiver, 48KHz

tr(CK)

I2S clock rise time

Capacitive load CL=30pF

tf(CK)

I2S clock fall time

tv(WS)

WS valid time

Master mode

th(WS)

WS hold time

Master mode

tsu(WS)

WS setup time

Slave mode

th(WS)

WS hold time

Slave mode

tsu(SD_MR) Data input setup time

Master receiver

tsu(SD_SR) Data input setup time

Slave receiver

th(SD_MR)

Data input hold time

Master receiver

th(SD_SR)

Slave receiver

tv(SD_ST) Data output valid time

Slave transmitter

(after enable edge)

-64

th(SD_ST) Data output hold time

Slave transmitter

(after enable edge)

tv(SD_MT) Data output valid time

Master transmitter

(after enable edge)

-12

th(SD_MT) Data output hold time

Master transmitter

(after enable edge)

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