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PI6CBF18501 Datasheet(PDF) 7 Page - Diodes Incorporated |
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PI6CBF18501 Datasheet(HTML) 7 Page - Diodes Incorporated |
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7 / 17 page ![]() 7 A Product Line of Diodes Incorporated PI6CBF18501 www.diodes.com October 2020 Diodes Incorporated PI6CBF18501 Document Number DS43130 Rev 2-2 HCSL Input Characteristics(1) Temperature = TA; Supply voltages per normal operation conditions; See test circuits for the load conditions Symbol Parameters Conditions Min. Typ. Max. Units VIHDIF Diff. Input High Voltage(3) IN+, IN-, single-end measurement 600 800 1150 mV VILDIF Diff. Input Low Voltage(3) IN+, IN-, single-end measurement -300 0 300 mV VCOM Diff. Input Common Mode Voltage 150 1000 mV VSWING Diff. Input Swing Voltage Peak to peak value (VIHDIF - VILDIF) 300 1450 mV fIN Input Frequency 1 200 MHz tSTAB Clock stabilization From VDD Power-Up and after input clock stabilization or de-assertion of PD# to 1st clock 0.6 1.0 ms tRF Diff. Input Slew Rate(2) Measured differentially 0.4 8 V/ns IIN Diff. Input Leakage Current VIN = VDD, VIN = GND -5 0.01 5 uA tDC Diff. Input Duty Cycle Measured differentially 45 55 % tjc-c Diff. Input Cycle to cycle jitter Measured differentially 125 ps Note: 1. Guaranteed by design and characterization, not 100% tested in production 2. Slew rate measured through +/-75mV window centered around differential zero 3. The device can be driven by a single-ended clock by driving the true clock and biasing the complement clock input to the Vbias, where Vbias is (VIH-VIL)/2 LVCMOS AC Electrical Characteristics Temperature = TA; Supply voltages per normal operation conditions; See test circuits for the load conditions Symbol Parameters Conditions Min. Typ. Max. Units tOELAT Output enable latency Q start after OE# assertion Q stop after OE# deassertion 1 3 clocks tPDLAT PD# de-assertion Differential outputs enable after PD# de- assertion 20 300 us |
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