Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

PI6CBF18501 Datasheet(PDF) 7 Page - Diodes Incorporated

Part # PI6CBF18501
Description  Very Low Power 5-Output PCIe Fanout Buffer With On-chip Termination
PDF  17 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  DIODES [Diodes Incorporated]
Direct Link  http://www.diodes.com
Logo DIODES - Diodes Incorporated

PI6CBF18501 Datasheet(HTML) 7 Page - Diodes Incorporated

Back Button PI6CBF18501 Datasheet HTML 3Page - Diodes Incorporated PI6CBF18501 Datasheet HTML 4Page - Diodes Incorporated PI6CBF18501 Datasheet HTML 5Page - Diodes Incorporated PI6CBF18501 Datasheet HTML 6Page - Diodes Incorporated PI6CBF18501 Datasheet HTML 7Page - Diodes Incorporated PI6CBF18501 Datasheet HTML 8Page - Diodes Incorporated PI6CBF18501 Datasheet HTML 9Page - Diodes Incorporated PI6CBF18501 Datasheet HTML 10Page - Diodes Incorporated PI6CBF18501 Datasheet HTML 11Page - Diodes Incorporated Next Button
Zoom Inzoom in Zoom Outzoom out
 7 / 17 page
background image
7
A Product Line of
Diodes Incorporated
PI6CBF18501
www.diodes.com
October 2020
Diodes Incorporated
PI6CBF18501
Document Number DS43130 Rev 2-2
HCSL Input Characteristics(1)
Temperature = TA; Supply voltages per normal operation conditions; See test circuits for the load conditions
Symbol Parameters
Conditions
Min.
Typ.
Max.
Units
VIHDIF
Diff. Input High Voltage(3)
IN+, IN-, single-end measurement
600
800
1150
mV
VILDIF
Diff. Input Low Voltage(3)
IN+, IN-, single-end measurement
-300
0
300
mV
VCOM
Diff. Input Common Mode
Voltage
150
1000
mV
VSWING
Diff. Input Swing Voltage
Peak to peak value (VIHDIF - VILDIF)
300
1450
mV
fIN
Input Frequency
1
200
MHz
tSTAB
Clock stabilization
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st
clock
0.6
1.0
ms
tRF
Diff. Input Slew Rate(2)
Measured differentially
0.4
8
V/ns
IIN
Diff. Input Leakage Current
VIN = VDD, VIN = GND
-5
0.01
5
uA
tDC
Diff. Input Duty Cycle
Measured differentially
45
55
%
tjc-c
Diff. Input Cycle to cycle jitter Measured differentially
125
ps
Note:
1. Guaranteed by design and characterization, not 100% tested in production
2. Slew rate measured through +/-75mV window centered around differential zero
3. The device can be driven by a single-ended clock by driving the true clock and biasing the complement clock input to the Vbias, where Vbias is (VIH-VIL)/2
LVCMOS AC Electrical Characteristics
Temperature = TA; Supply voltages per normal operation conditions; See test circuits for the load conditions
Symbol
Parameters
Conditions
Min.
Typ.
Max.
Units
tOELAT
Output enable latency
Q start after OE# assertion
Q stop after OE# deassertion
1
3
clocks
tPDLAT
PD# de-assertion
Differential outputs enable after PD# de-
assertion
20
300
us



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com