71M6532DSLASHF datasheet(39/121 Pages) MAXIM

39 / 121 page

FDS 6531/6532 005

Data Sheet 71M6531D/F-71M6532D/F

Rev 2

The MPU cannot write to flash while the CE is executing its code from flash. Two interrupts warn of collisions

between the MPU firmware and the CE timing. If a flash write operation is attempted while the CE is

busy, the flash write will not execute and the FWCOL0 interrupt will be issued. If a flash write is still in

progress when the CE would otherwise begin a code pass, the code pass is skipped, the write operation

is completed, and the FWCOL1 interrupt is issued.

The simplest flash write procedure disables the CE during the write operation and interpolates the metering

measurements. However, this results in the loss of at least one second of data, because the CE has to

resynchronize with the mains voltage.

There is a brief guaranteed interval (typically 1/32768 s) between CE executions which occurs 2520 times

per second. The start of the interval can be detected with the CE_BUSY interrupt which occurs on the

falling edge of CE_BUSY (an internal signal measurable from TMUXOUT). However, this guaranteed idle

time (30.5 µs) is too short to write a byte which takes 42 µs or to erase a page of flash memory which

takes at least 20 ms. Some CE code has substantially longer idle times, but in those cases, firmware

interrupt latencies can easily consume the available write time. If a flash write fails in this scheme, the

failure can be detected with the FWCOL0 or FWCOL1 interrupt and the write can be retried.

It is practical to pre-erase pages, disable interrupts and poll the CE_BUSY interrupt flag, IRCON[2]. This

method avoids problems with interrupt latency, but can still result in a write failure if the CE code takes to

much time. As mentioned above, polling FWCOL0 and FWCOL1 can detect write failures. However, the

speed in a polling write is only 2520 bytes per second and the firmware cannot respond to interrupts.

As an alternative to using flash, a small EEPROM can store data without compromises. EEPROM interfaces

are included in the device.

Updating Individual Bytes in Flash Memory

The original state of a flash byte is 0xFF (all ones). Once a value other than 0xFF is written to a flash

memory cell, overwriting with a different value usually requires that the cell be erased first. Since cells

cannot be erased individually, the page has to be copied to RAM, followed by a page erase. After this,

the page can be updated in RAM and then written back to the flash memory.

Flash Erase Procedures

Flash erasure is initiated by writing a specific data pattern to specific SFR registers in the proper sequence.

These special pattern/sequence requirements prevent inadvertent erasure of the flash memory.

The mass erase sequence is:

1. Write 1 to the FLSH_MEEN bit (SFR 0xB2[1]).

2. Write pattern 0xAA to FLSH_ERASE (SFR 0x94).

The mass erase cycle can only be initiated when the ICE port is enabled.

The page erase sequence is:

1. Write the page address to FLSH_PGADR[5:0] (SFR 0xB7[7:1]).

2. Write pattern 0x55 to FLSH_ERASE (SFR 0x94).

Note: Transitions to BROWNOUT mode must be avoided during page erase operations.

Bank-Switching:

The program memory of the 71M6531 consists of a fixed lower bank of 32 KB addressable at 0x0000 to

0x7FFF plus an upper bank area of 32 KB, addressable at 0x8000 to 0xFFFF. The upper 32 KB space is

banked using the I/O RAM FL_BANK register as follows:

•

The 71M6531D provides 4 banks of 32 KB each selected by FL_BANK[1:0]. Note that when

FL_BANK[1:0] = 00, the upper bank is the same as the lower bank.

•

The 71M6531F and 71M6532D/F provide 8 banks of 32 KB each selected by FL_BANK[2:0].

Table 38 illustrates the bank switching mechanism.

71M6532D/F Datasheet(PDF) 39 Page - Maxim Integrated Products

71M6532D/F Datasheet(HTML) 39 Page - Maxim Integrated Products

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL