71M6532DSLASHF datasheet(40/121 Pages) MAXIM

40 / 121 page

Data Sheet 71M6531D/F-71M6532D/F

FDS 6531/6532 005

Rev 2

Table 38: Bank Switching with FL_BANK[2:0]

71M6531D

FL_BANK [1:0]

71M653XF

FL_BANK [2:0]

Address Range for Lower

Bank (0x000-0x7FFF)

Address Range for Upper

Bank (0x8000-0xFFFF)

000

0x0000-0x7FFF

001

0x8000-0xFFFF

010

0x10000-0x17FFF

011

0x18000-0x1FFFF

100

0x20000-0x217FF

101

0x28000-0x2FFFF

110

0x30000-0x37FFF

111

0x38000-0x3FFFF

Program Security

When enabled, the security feature limits the ICE to global flash erase operations only. All other ICE

operations are blocked. This guarantees the security of the user’s MPU and CE program code. Security

should be enabled by MPU code that is executed during the pre-boot interval (60 CKMPU cycles before

the primary boot sequence begins). Once security is enabled, the only way to disable it is to perform a

global erase of the flash, followed by a chip reset.

The first 60 cycles of the MPU boot code are called the pre-boot phase because during this phase the

ICE is inhibited. A read-only status bit, PREBOOT, identifies these cycles to the MPU. Upon completion

of pre-boot, the ICE can be enabled and is permitted to take control of the MPU.

The security enable bit, SECURE, is reset whenever the chip is reset. Hardware associated with the bit

permits only ones to be written to it. Thus, pre-boot code may set SECURE to enable the security feature

but may not reset it. Once SECURE is set, the pre-boot code is protected and no external read of program

code is possible

Specifically, when SECURE is set, the following applies:

•

The ICE is limited to bulk flash erase only.

•

Page zero of flash memory, the preferred location for the user’s pre-boot code, may not be

page-erased by either MPU or ICE. Page zero may only be erased with global flash erase.

•

Write operations to page zero, whether by MPU or ICE are inhibited.

MPU/CE RAM:

The 71M6531D/F and 71M6532D/F include 4 KB of static RAM memory on-chip (XRAM) plus 256-bytes

of internal RAM in the MPU core. The 4 KB of static RAM are used for data storage for MPU and CE

operations.

1.5.6 Optical Interface

The device includes an interface to implement an IR/optical port. The pin OPT_TX is designed to directly

drive an external LED for transmitting data on an optical link. The pin OPT_RX has the same threshold

as the RX pin, but can also be used to sense the input from an external photo detector used as the receiver

for the optical link. OPT_TX and OPT_RX are connected to a dedicated UART port (UART1).

The OPT_TX and OPT_RX pins can be inverted with configuration bits OPT_TXINV and OPT_RXINV,

respectively. Additionally, the OPT_TX output may be modulated at 38 kHz. Modulation is available when

system power is present (i.e. not in BROWNOUT mode). The OPT_TXMOD bit enables modulation. Duty

cycle is controlled by OPT_FDC[1:0], which can select 50%, 25%, 12.5% and 6.25% duty cycle. 6.25% duty

cycle means OPT_TX is low for 6.25% of the period. Figure 9 illustrates the OPT_TX generator.

When not needed for the optical UART, the OPT_TX pin can alternatively be configured as DIO2,

WPULSE, or VARPULSE. The configuration bits are OPT_TXE[1:0]. Likewise, OPT_RX can alternately

be configured as DIO1. Its control is OPT_RXDIS.

71M6532D/F Datasheet(PDF) 40 Page - Maxim Integrated Products

71M6532D/F Datasheet(HTML) 40 Page - Maxim Integrated Products

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL