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SIP4282 Datasheet(PDF) 8 Page - Vishay Siliconix |
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SIP4282 Datasheet(HTML) 8 Page - Vishay Siliconix |
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8 / 13 page ![]() SiP4282, SiP4282A www.vishay.com Vishay Siliconix S20-0532-Rev. H, 06-Jul-2020 8 Document Number: 65740 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 DETAILED DESCRIPTION The SiP4282 is a p-channel MOSFET power switches designed for high-side slew rate controlled load-switching applications. Once turned on, the slew-rate control circuitry is activated and current is ramped in a linear fashion until it reaches the level required for the output load condition. This is accomplished by first elevating the gate voltage of the MOSFET up to its threshold voltage and then by linearly increasing the gate voltage until the MOSFET becomes fully enhanced. At this point, the gate voltage is then quickly increased to the full input voltage to reduce RDS(on) of the MOSFET switch and minimize any associated power losses. All versions features a shutdown output discharge circuit which is activated at shutdown (when the part is disabled through the on / off pin) and discharges the output pin through a small internal resistor hence, turning off the load. For SiP4282-3, in instances where the input voltage falls below 1.4 V (typically) the under voltage lock-out circuitry protects the MOSFET switch from entering the saturation region or operation by shutting down the chip. APPLICATION INFORMATION Input Capacitor While a bypass capacitor on the input is not required, a 1 μF or larger capacitor for CIN is recommended in almost all applications. The bypass capacitor should be placed as physically close as possible to the SiP4282 to be effective in minimizing transients on the input. Ceramic capacitors are recommended over tantalum because of their ability to withstand input current surges from low impedance sources such as batteries in portable devices. Output Capacitor A 0.1 μF capacitor or larger across VOUT and GND is recommended to insure proper slew operation. COUT may be increased without limit to accommodate any load transient condition with only minimal affect on the SiP4282 turn on slew rate time. There are no ESR or capacitor type requirement. Enable The on / off pin is compatible with both TTL and CMOS logic voltage levels. Protection Against Reverse Voltage Condition The p-channel MOSFET pass transistor has an intrinsic diode that is reversed biased when the input voltage is greater than the output voltage. Should VOUT exceed VIN, this intrinsic diode will become forward biased and allow excessive current to flow into the IC thru the VOUT pin and potentially damage the IC device. Therefore extreme care should be taken to prevent VOUT from exceeding VIN. In conditions where VOUT exceeds VIN a Schottky diode in parallel with the internal intrinsic diode is recommended to protect the SiP4282. Thermal Considerations The SiP4282 is designed to maintain a constant output load current. Due to physical limitations of the layout and assembly of the device the maximum switch current is 1.2 A, as stated in the Absolute Maximum Ratings table. However, another limiting characteristic for the safe operating load current is the thermal power dissipation of the package. To obtain the highest power dissipation (and a thermal resistance of 90 °C/W) the power pad of the device should be connected to a heat sink on the printed circuit board. The maximum power dissipation in any application is dependent on the maximum junction temperature, TJ (max.) = 125 °C, the junction-to-ambient thermal resistance for the SC-75 PPAK package, J-A = 90 °C/W, and the ambient temperature, TA, which may be formulaically expressed as: It then follows that, assuming an ambient temperature of 70 °C, the maximum power dissipation will be limited to about 610 mW. So long as the load current is below the 1.2 A limit, the maximum continuous switch current becomes a function two things: the package power dissipation and the RDS(on) at the ambient temperature. As an example let us calculate the worst case maximum load current at TA = 70 °C. The worst case RDS(on) at 25 °C occurs at an input voltage of 1.8 V and is equal to 480 m . The RDS(on) at 70 °C can be extrapolated from this data using the following formula RDS(on) (at 70 °C) = RDS(on) (at 25 °C) x (1 + TC x T) Where TC is 3300 ppm/°C. Continuing with the calculation we have RDS(on) (at 70 °C) = 480 m x (1 + 0.0033 x (70 °C - 25 °C)) = 551 m The maximum current limit is then determined by which in case is 1.05 A. Under the stated input voltage condition, if the 1.05 A current limit is exceeded the internal die temperature will rise and eventually, possibly damage the device. P (max.) T J (max.) - TA J-A ------------------------------------- 125 - T A 90 ----------------------- == I LOAD (max.) P (max.) R DS(on) ----------------------- |
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