AD4030-24BBCZ datasheet(21/48 Pages) AD

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Data Sheet

AD4030-24

THEORY OF OPERATION

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Full-Scale Saturation

The conversion results saturate digitally (before any post-process-

ing) when either or both inputs exceed the analog limits specified

herein. After applying offset and gain scaling, the results are trun-

cated to 24-bit representation (saturating at maximum 0x7FFFFF

and minimum 0x800000). Care must be taken to avoid unintentional

saturation, especially when applying digital offset and/or gain scal-

ing. See the Digital Offset Adjust and Digital Gain sections for more

details on the use of these features.

Common-Mode Output

When the host controller writes 0x1 or 0x2 to the OUT_DATA_MD

bit field of the modes register (see the Modes Register section),

an 8-bit code representing the input common-mode voltage is

appended to the 16-bit or 24-bit code representing the input voltage

difference. The LSB size of the 8-bit code is VREF/256. The 8-bit

code saturates at 0 and 255 when the common mode input voltage

is 0 V and VREF, respectively. The 8-bit code is not affected by

digital offset and gain scaling, which is applied only to the code

representing the input voltage difference.

Block Averaging

The AD4030-24 provides a block averaging filter (SINC1) with

programmable block length 2N, N = 1, 2, 3, …, 16. The filter is reset

after processing each block of 2N samples. The filter is enabled by

writing 0x3 to the OUT_DATA_MD bit field of the modes register

(see the Modes Register section) as well as a value (1 ≤ N ≤

16) to the AVG_VAL bit field in the averaging mode register (see

the Averaging Mode Register section). In this configuration, the

output sample word is 32 bits. The 30 most significant bits (MSBs)

represent the numerical value of the 24-bit codes averaged in

blocks of 2N samples. The automatic scaling allows the 24 MSBs of

the 30-bit code are equal to the 24-bit codes when averaging blocks

of constant values. The 31st bit (OR) is an overrange warning bit

that is high when one or more samples in the block are subject to

saturation. The 32nd bit (SYNC) is high once every 2N conversion

cycles to indicate when the average values are updated at the

end of each block of samples. See the Digital Sample Processing

Features section for more information.

The effective data rate in averaging mode is fCNV/2N. The reset

value of N in the AVG_VAL bit field is 0x00 (no averaging). Figure

54 shows an example timing diagram in averaging mode. Figure 39

shows the frequency response of the filter for an N = 1, 2, 3, 4, 5.

Figure 39. Frequency Response Examples for the Block Averaging Filter

Digital Offset Adjust

The ADC can be programmed to add a 24-bit signed offset value

to the sample data (see the Register Details section). When adding

an offset to the samples, it is possible to cause the sample data

to saturate numerically. The user must take this into account when

using the offset feature. The default value is 0x000000. See the

Offset Registers section for more details.

Digital Gain

The ADC can be programmed to apply a 16-bit unsigned digital

gain (Register 0x1C and Register 0x1D) to the digital samples (see

the Register Details section). The gain is applied to each sample

based on the following equation:

CodeOUT = CodeIN × (USER_GAIN/0x8000)

where:

0x0000 ≤ USER_GAIN ≤ 0xFFFF.

The effective gain range is 0 to 1.99997. Note that applying gain to

the samples may cause numerical saturation. The default value is

0x8000 (gain = 1). To measure input voltage differences exceeding

±VREF, set the gain less than the unity to avoid the numerical

saturation of the 24-bit, 16-bit, or 30-bit output differential codes.

See the Gain Registers section for more details.

Test Pattern

To facilitate functional testing and debugging of the SPI, the host

controller can write a 32-bit test pattern to the AD4030-24 (see

the Test Pattern Registers section). The value written to the test

pattern registers is output using the normal sample cycle timing.

The 32-bit test pattern output mode is enabled by writing 0x4 to

the OUT_DATA_MD bit field of the modes register (see the Modes

registers is 0x5A5A0F0F.

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