SSM6515 datasheet(21/40 Pages) AD

21 / 40 page

Data Sheet

SSM6515

THEORY OF OPERATION

analog.com

Rev. 0 | 21 of 40

I2C Read and Write Operations

Figure 36 shows the timing of a single-word write operation. Every

ninth clock, the SSM6515 issues an acknowledge by pulling SDA

low.

Figure 37 shows the timing of a burst mode write sequence. Figure

37 shows an example in which the target destination registers are

two bytes. The SSM6515 increments its subaddress register every

byte because the requested subaddress corresponds to a register

or memory area with a byte word length.

The timing of a single word read operation is shown in Figure

38. The first R/W bit is 0, indicating a write operation followed

by the subaddress of the register to be read. After the SSM6515

acknowledges the receipt of the subaddress, the master must issue

a repeated start command followed by the chip address byte with

the R/W set to 1 (read). The SSM6515 acknowledges and puts 8-bit

data on the SDA pin. The master then responds every ninth pulse

with an acknowledge pulse to the SSM6515.

Figure 36 through Figure 39 use the following abbreviations:

►

S is the start bit

►

P is the stop bit

►

AM is the acknowledge by master

►

AS is the acknowledge by slave

Figure 36. Single Word I2C Write Format

Figure 37. Burst Mode I2C Write Format

Figure 38. Single Word I2C Read Format

Figure 39. Burst Mode I2C Read Format

SSM6515 Datasheet(PDF) 21 Page - Analog Devices