MMPF0100_V01 datasheet(22/137 Pages) NXP

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NXP Semiconductors

PF0100

FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

6.1.2.2

PWRON pin configuration

The PWRON pin can be configured as either a level sensitive input (PWRON_CFG = 0), or as an edge sensitive input

(PWRON_CFG = 1). As a level sensitive input, an active high signal turns on the part and an active low signal turns off the part, or puts it

into sleep mode. As an edge sensitive input, such as when connected to a mechanical switch, a falling edge turns on the part and if the

switch is held low for greater than or equal to 4.0 seconds, the part turns off or enters sleep mode.

6.1.2.3

I2C address configuration

The I2C device address can be programmed from 0x08 to 0x0F. This allows flexibility to change the I2C address to avoid bus conflicts.

Address bit, I2C_SLV_ADDR[3] in OTP_I2C_ADDR register is hard coded to “1” while the lower three LSBs of the I2C address

(I2C_SLV_ADDR[2:0]) are programmable as shown in Table 15.

Table 12. Start-up sequence

SWxx_SEQ[4:0]/

VGENx_SEQ[4:0]/

VREFDDR_SEQ[4:0]

Sequence

00000

Off

00001

SEQ_CLK_SPEED[1:0] * 1

00010

SEQ_CLK_SPEED[1:0] * 2

11111

SEQ_CLK_SPEED[1:0] * 31

Table 13. Start-up sequence clock speed

SEQ_CLK_SPEED[1:0]

Time (

μs)

500

1000

2000

4000

Table 14. PWRON configuration

PWRON_CFG

Mode

PWRON pin HIGH = ON

PWRON pin LOW = OFF or Sleep mode

PWRON pin pulled LOW momentarily = ON

PWRON pin LOW for 4.0 seconds = OFF or Sleep mode

Table 15. I2C address configuration

I2C_SLV_ADDR[3]

hard coded

I2C_SLV_ADDR[2:0]

I2C device address

(Hex)

000

0x08

001

0x09

010

0x0A

011

0x0B

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