8

SMS44

2047 2.3 10/23/00

SUMMIT MICROELECTRONICS, Inc.

Table 7. PUP Delays

Longdog timer will generally be programmed to be of

longer duration than the watchdog and it will generate a

reset if it times out. Both timers are cleared by a low to high

transition on WLDI and they both start simultaneously.

If the watchdog should timeout the device status will be

recorded in the status register. If the Longdog times out

RESET# will drive low either until a WLDI clear is received

return high. Refer to Figures 3 and 4 illustrating the action

of RESET# and IRQ# with respect to the Watchdog and

Longdog timers and the WLDI input.

If WLDI is held low the timers will free-run generating a

series of interrupts and resets. If WLDI is held high the

interrupt (watchdog) output will be disabled and only the

reset (Longdog) output will be active.

2047 Table04 1.0

7

B

S

M

65

4

3

2

1

0

B

S

L

Q

E

S1

O

T

R0

O

T

R1

D

L0

D

L

2

D

W1

D

W0

D

W

xxx

0

0

f

f

O

g

o

d

g

n

o

L

xxx

0

1

s

m

0

0

6

1

xxx

1

0

s

m

0

0

2

3

xxx

1

1

s

m

0

0

4

6

x0

0

x

x

t

O

T

R

P

s

m

5

2

=

x0

1

x

x

t

O

T

R

P

s

m

0

5

=

x1

0

x

x

t

O

T

R

P

s

m

0

0

1

=

x1

1

x

x

t

O

T

R

P

s

m

0

0

2

=

0x

x

x

x

n

O

e

c

n

e

u

q

e

S

1x

x

x

x

f

f

O

e

c

n

e

u

q

e

S

Table 4. Configuration Register 6

When the Longdog times out, a reset will be generated.

strobe) both timers are reset to time zero. Therefore, if the

it can drive the output low.

Register 6 is also used to set the programmable reset

Sequence Delay Programming

The sequence delays are programmed in register 7. Bit 7

of register 6, must be set to a “0” in order to enable the

sequencing of the PUP# outputs. Sequencing will not

Each PUP# (-3, -2 and -1) is delayed according to the

states of its Bit 1 and Bit 0 as indicated in Table 7.

Refer to Figures 5 and 6 for the detailed timing relationship

of the programmable power-on sequencing.

2047 Table06 1.0

2047 Table07 1.0

7

B

S

M

65432

1

0

B

S

L

Q

E

S1

O

T

R0

O

T

R1

D

L0

D

L

2

D

W1

D

W0

D

W

F

F

O

000

s

m

0

0

40

1

1

s

m

0

0

81

0

0

s

m

0

0

6

11

0

1

s

m

0

0

2

31

1

0

s

m

0

0

4

6

111

2047 Table05 1.0

Table 5. Configuration Register 6

Table 6. Configuration Register 7

1

t

i

B0

t

i

Bt

Y

L

D

P

X

00

y

a

l

e

D

)

o

n

(

s

m

0

01

y

a

l

e

D

s

m

5

2

10

y

a

l

e

D

s

m

0

5

11

y

a

l

e

D

s

m

0

0

1

7

B

S

M

65

4

3

2

1

0

B

S

L

s

s

e

r

d

d

A

t

c

e

l

e

S

e

t

a

t

S

#

P

U

P

3

#

P

U

P2

#

P

U

P1

#

P

U

P

k

c

o

L0

S

A

10

10

1

0

x

0

s

d

n

o

p

s

e

r

,

0

1

0

1

s

s

e

r

d

d

a

e

p

y

t

e

c

i

v

e

D

s

n

o

i

t

a

n

i

b

m

o

c

1

A

&

2

A

d

e

s

a

i

b

o

t

y

l

n

o

x

1

s

d

n

o

p

s

e

r

,

1

1

0

1

s

s

e

r

d

d

a

e

p

y

t

e

c

i

v

e

D

s

n

o

i

t

a

n

i

b

m

o

c

1

A

&

2

A

d

e

s

a

i

b

o

t

y

l

n

o

0

xd

e

l

b

a

n

e

e

t

i

r

w

/

d

a

e

r

n

o

i

t

a

r

u

g

i

f

n

o

C

1

xt

u

o

d

e

k

c

o

l

e

t

i

r

w

/

d

a

e

r

n

o

i

t

a

r

u

g

i

f

n

o

C