PCA9541ADSLASH01 datasheet(10/45 Pages) NXP

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PCA9541A

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Product data sheet

Rev. 5 — 24 April 2014

10 of 45

NXP Semiconductors

PCA9541A

2-to-1 I2C-bus master selector with interrupt logic and reset

7.3.1 Register 0: Interrupt Enable (IE) register (B1:B0 = 00b)

This register allows a master to read and/or write (if needed) Mask options for its own

channel.

The Interrupt Enable register described below is identical for both the masters.

Nevertheless, there are physically 2 internal Interrupt Enable registers, one for each

upstream channel. When Master 0 reads/writes in this register, the internal Interrupt

Enable Register 0 is accessed. When Master 1 reads/writes in this register, the internal

Interrupt Enable Register 1 is accessed.

[1]

Default values are the same for PCA9541A/01, PCA9541A/03.

Table 5.

BUSLOSTMSK

BUSOKMSK

BUSINITMSK

INTINMSK

Table 6.

Legend: * default value

Bit

Symbol

Access Value[1] Description

7:4

R only

not used

BUSLOSTMSK

R/W

An interrupt on INT will be generated after the other master has been

disconnected.

An interrupt on INT will not be generated after the other master has been

disconnected.

BUSOKMSK

R/W

After connection is requested and Bus Initialization not requested

(BUSINIT = 0), an interrupt on INT will be generated when a non-idle situation

has been detected on the downstream slave channel by the bus sensor at the

switching moment.

Remark: Channel switching is done automatically after the STOP command.

After connection is requested and Bus Initialization not requested

(BUSINIT = 0), an interrupt on INT will not be generated when a non-idle

situation has been detected on the downstream slave channel by the bus

sensor at the switching moment (masked).

Remark: Channel switching is done automatically after the STOP command.

BUSINITMSK

R/W

After connection is requested and Bus Initialization requested (BUSINIT = 1),

an interrupt on INT will be generated when the bus initialization is done.

Remark: Channel switching is done after bus initialization completed.

After connection is requested and Bus Initialization requested (BUSINIT = 1),

an interrupt on INT will not be generated when the bus initialization is done

(masked).

Remark: Channel switching is done after bus initialization completed.

INTINMSK

R/W

Interrupt on INT_IN generates an interrupt on INT.

Interrupt on INT_IN does not generate an interrupt on INT (masked)

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