TUSB1104 datasheet(11/55 Pages) TI

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5.7 USB Electrical Characteristics (continued)

over operating free-air temperature and voltage range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CPLF-LINRL0

Low-frequency -1dB compression

point at LINR_L0 setting.

20 MHz clock pattern; VID is 200 mV to

1200 mV in 10 mV steps;

750

mVpp

CPHF-LINRL0

High-frequency -1dB compression

point at LINR_L0 setting.

5 GHz clock pattern; VID is 200mV to

1200mV in 10mV steps;

650

mVpp

CPLF-LINRL1

Low-frequency -1dB compression

point at LINR_L1 setting.

20 MHz clock pattern; VID is 200 mV to

1200 mV in 10 mV steps;

850

mVpp

CPHF-LINRL1

High-frequency -1dB compression

point at LINR_L1 setting.

5 GHz clock pattern; VID is 200 mV to

1200 mV in 10 mV steps;

750

mVpp

CPLF-LINRL2

Low-frequency -1dB compression

point at LINR_L2 setting.

20 MHz clock pattern; VID is 200 mV to

1200 mV in 10 mV steps;

950

mVpp

CPHF-LINRL2

High-frequency -1dB compression

point at LINR_L2 setting.

5 GHz clock pattern; VID is 200 mV to

1200 mV in 10 mV steps;

850

mVpp

CPLF-LINRL3

Low-frequency -1dB compression

point at LINR_L3 setting.

20 MHz clock pattern; VID is 200 mV to

1200 mV in 10mV steps;

1050

mVpp

CPHF-LINRL3

High-frequency -1dB compression

point at LINR_L3 setting.

5 GHz clock pattern; VID is 200 mV to

1200 mV in 10 mV steps;

900

mVpp

fLF

Low frequency cutoff

200 mVPP< VID < 1200 mVPP

kHz

tTX_DJ_SSTX2-CTX2

TX output deterministic residual jitter

SSTX2-> CTX2.

Optimal EQ setting; 12-in prechannel

(SDD21 = -11.2 dB); 1.6-in post channel

(SDD21 = -1.8 dB); PRBS7; 10 Gbps

.05

tTX_DJ_SSTX1-CTX1

TX output deterministic residual jitter

SSTX1-> CTX1.

Optimal EQ setting; 12-in prechannel

(SDD21 = -11.2 dB); 1.6-in post channel

(SDD21 = -1.8 dB); PRBS7; 10 Gbps

.05

5.8 Timing Requirements

MIN

NOM

MAX

UNIT

USB3.1

tIDLEEntry

Delay from U0 to electrical idle

Refer to Figure 6-4.

tIDELExit_U1

U1 exit time: break in electrical idle to the

transmission of LFPS

Refer to Figure 6-4.

tIDLEExit_U2U3

U2/U3 exit time: break in electrical idle to

transmission of LFPS

Refer to Figure 6-4.

µs

tRXDET_INTVL

RX detect interval while in Disconnect

tIDLEExit_DISC

Disconnect Exit Time

µs

tExit_SHTDN

Shutdown Exit Time

0.75

tAEQ_FULL_DONE

Maximum time to obtain optimum EQ setting

when operating in Full AEQ mode.

400

µs

tAEQ_FAST_DONE

Maximum time to determine appropriate EQ

setting when operating in Fast AEQ mode.

µs

tDIFF_DLY

Differential Propagation Delay

Refer to Figure 6-3.

300

tR, tF

Output Rise/Fall time

20%-80% of differential voltage

measured 1.7 inch from the

output pin; Refer to Figure 6-5.

tRF_MM

Output Rise/Fall time mismatch

20%-80% of differential voltage

measured 1.7 inch from the

output pin

2.6

Power-up

tEN_LOW

EN pin held low after supply reaches VCC(min) Refer to Figure 6-1

tCFG_SU

CFG(1) high

Refer to Figure 6-1

250

µs

tCFG_HD

CFG(1) high

Refer to Figure 6-1

500

µs

(1)

Following pins comprise CFG pins: MODE, CEQ[1:0], SSEQ[1:0], EQCFG, AEQCFG

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TUSB1104

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